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RISC-V Fixes for 4.2-rc2

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This contains a handful of patches that I'd like to target for 4.2:
 
 * OpenSBI upgrade to 0.5
 * Increase in the flash size of the virt board.
 * A non-functional cleanup.
 * A cleanup to our MIP handling that avoids atomics.
 
 This passes "make check" and boots OpenEmbedded for me.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAl3Nn18THHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQQYxEACVIdVobMaddZC1tUhzyY9Ef2AzRqca
 GyyHIyMlmVzOhHOD0Rig4HQWGzvxSxmzrNNYc0N0kh7IsnVUkOLyROv5tvSpMLpb
 hyLwMcIWTNWVLraAZ/e/TTwkzKenXB2gvl5ny00LhUW4Lt0lwkFgB6SMtL1R5K+r
 HYYeiWPXbMfUnft/zpdTN0mT4Y8+gUai6XK83QOuwZohsAepBvKDVJD5uORZ6gZK
 hQfaWZ/FzMDDC0BeQtt7NN6ElLJjilzESxgoDoLrcpq2BfmSWMo4XKH/k9DzNTbi
 iWqel1q/lirxclglqjYFDuqhb37gfHYtPqQG+jZ5+7YVuyVhB6+dRIIGbzp5Jrv5
 0DcKmmI51ngKpiWcos70AJh+inM5fRgEhW024IntInwn0Y8aEpTo4YAAXUIMQleF
 3An9CSjXuxHSdtJItIJtLLGhaV7i2k5xRWIM+hgpUcW2sYqUdfB0URp+pEg2Y/4k
 1btPXfWLbd0AGlXMwVv6QYdaKKhFE+0XcIK+HqsIec0qQlJ0lksdNJyNQTsxqCfP
 mQugcBwZJp/4RoMrT14RMFhPfAZjZAEZuh3IKBCMoKui4RS51YF6MNXevR2J5VYK
 BNotdb2+ceEtLOnaKReqYzXtl6MuSzLmPWKZrrA3l/CdtKXkAd6IUhjNvrNz5Nie
 cZyV3qhagZ3P3Q==
 =vwgx
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc2' into staging

RISC-V Fixes for 4.2-rc2

This contains a handful of patches that I'd like to target for 4.2:

* OpenSBI upgrade to 0.5
* Increase in the flash size of the virt board.
* A non-functional cleanup.
* A cleanup to our MIP handling that avoids atomics.

This passes "make check" and boots OpenEmbedded for me.

# gpg: Signature made Thu 14 Nov 2019 18:39:27 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-rc2:
  riscv/virt: Increase flash size
  opensbi: Upgrade from v0.4 to v0.5
  target/riscv: Remove atomic accesses to MIP CSR
  remove unnecessary ifdef TARGET_RISCV64

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-11-15 11:22:33 +00:00
commit 19bef037fe
10 changed files with 24 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/riscv/virt.c
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@ -62,7 +62,7 @@ static const struct MemmapEntry {
[VIRT_PLIC] = { 0xc000000, 0x4000000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FLASH] = { 0x20000000, 0x2000000 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },

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pc-bios/opensbi-riscv32-virt-fw_jump.bin
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pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
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pc-bios/opensbi-riscv64-virt-fw_jump.bin
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2
roms/opensbi

@ -1 +1 @@
Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6
Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09

5
target/riscv/cpu.c
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@ -224,8 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
(target_ulong)atomic_read(&env->mip));
qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
@ -275,7 +274,7 @@ static bool riscv_cpu_has_work(CPUState *cs)
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
*/
return (atomic_read(&env->mip) & env->mie) != 0;
return (env->mip & env->mie) != 0;
#else
return true;
#endif

9
target/riscv/cpu.h
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@ -121,15 +121,6 @@ struct CPURISCVState {
target_ulong mhartid;
target_ulong mstatus;
/*
* CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
* by I/O threads. It should be read with atomic_read. It should be updated
* using riscv_cpu_update_mip with the iothread mutex held. The iothread
* mutex must be held because mip must be consistent with the CPU inturrept
* state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
* wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
* mip is 32-bits to allow atomic_read on 32-bit hosts.
*/
uint32_t mip;
uint32_t miclaim;

48
target/riscv/cpu_helper.c
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@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
@ -38,7 +39,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
target_ulong pending = atomic_read(&env->mip) & env->mie;
target_ulong pending = env->mip & env->mie;
target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
target_ulong irqs = (pending & ~env->mideleg & -mie) |
@ -92,42 +93,29 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
}
}
struct CpuAsyncInfo {
uint32_t new_mip;
};
static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state,
run_on_cpu_data data)
{
struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr;
if (info->new_mip) {
cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
}
g_free(info);
}
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
struct CpuAsyncInfo *info;
uint32_t old, new, cmp = atomic_read(&env->mip);
uint32_t old = env->mip;
bool locked = false;
do {
old = cmp;
new = (old & ~mask) | (value & mask);
cmp = atomic_cmpxchg(&env->mip, old, new);
} while (old != cmp);
if (!qemu_mutex_iothread_locked()) {
locked = true;
qemu_mutex_lock_iothread();
}
info = g_new(struct CpuAsyncInfo, 1);
info->new_mip = new;
env->mip = (env->mip & ~mask) | (value & mask);
async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async,
RUN_ON_CPU_HOST_PTR(info));
if (env->mip) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
if (locked) {
qemu_mutex_unlock_iothread();
}
return old;
}

2
target/riscv/csr.c
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@ -579,7 +579,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
} else {
old_mip = atomic_read(&env->mip);
old_mip = env->mip;
}
if (ret_value) {

4
target/riscv/translate.c
View File

@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = {
[0] = MO_SB,
[1] = MO_TESW,
[2] = MO_TESL,
[3] = MO_TEQ,
[4] = MO_UB,
[5] = MO_TEUW,
#ifdef TARGET_RISCV64
[3] = MO_TEQ,
[6] = MO_TEUL,
#endif
};
#endif