target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Filip Navara
Aurelien Jarno
parent
a6445c52aa
commit
194576157a
@ -338,12 +338,6 @@ DEF_HELPER_2(neon_qneg_s8, i32, env, i32)
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DEF_HELPER_2(neon_qneg_s16, i32, env, i32)
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DEF_HELPER_2(neon_qneg_s16, i32, env, i32)
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DEF_HELPER_2(neon_qneg_s32, i32, env, i32)
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DEF_HELPER_2(neon_qneg_s32, i32, env, i32)
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DEF_HELPER_0(neon_trn_u8, void)
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DEF_HELPER_0(neon_trn_u16, void)
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DEF_HELPER_0(neon_unzip_u8, void)
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DEF_HELPER_0(neon_zip_u8, void)
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DEF_HELPER_0(neon_zip_u16, void)
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DEF_HELPER_2(neon_min_f32, i32, i32, i32)
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DEF_HELPER_2(neon_min_f32, i32, i32, i32)
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DEF_HELPER_2(neon_max_f32, i32, i32, i32)
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DEF_HELPER_2(neon_max_f32, i32, i32, i32)
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DEF_HELPER_2(neon_abd_f32, i32, i32, i32)
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DEF_HELPER_2(neon_abd_f32, i32, i32, i32)
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@ -495,61 +495,3 @@ uint64_t HELPER(neon_sub_saturate_u64)(uint64_t src1, uint64_t src2)
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}
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}
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return res;
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return res;
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}
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}
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/* These need to return a pair of value, so still use T0/T1. */
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/* Transpose. Argument order is rather strange to avoid special casing
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the tranlation code.
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On input T0 = rm, T1 = rd. On output T0 = rd, T1 = rm */
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void HELPER(neon_trn_u8)(void)
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{
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uint32_t rd;
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uint32_t rm;
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rd = ((T0 & 0x00ff00ff) << 8) | (T1 & 0x00ff00ff);
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rm = ((T1 & 0xff00ff00) >> 8) | (T0 & 0xff00ff00);
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T0 = rd;
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T1 = rm;
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}
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void HELPER(neon_trn_u16)(void)
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{
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uint32_t rd;
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uint32_t rm;
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rd = (T0 << 16) | (T1 & 0xffff);
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rm = (T1 >> 16) | (T0 & 0xffff0000);
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T0 = rd;
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T1 = rm;
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}
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/* Worker routines for zip and unzip. */
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void HELPER(neon_unzip_u8)(void)
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{
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uint32_t rd;
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uint32_t rm;
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rd = (T0 & 0xff) | ((T0 >> 8) & 0xff00)
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| ((T1 << 16) & 0xff0000) | ((T1 << 8) & 0xff000000);
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rm = ((T0 >> 8) & 0xff) | ((T0 >> 16) & 0xff00)
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| ((T1 << 8) & 0xff0000) | (T1 & 0xff000000);
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T0 = rd;
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T1 = rm;
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}
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void HELPER(neon_zip_u8)(void)
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{
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uint32_t rd;
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uint32_t rm;
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rd = (T0 & 0xff) | ((T1 << 8) & 0xff00)
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| ((T0 << 16) & 0xff0000) | ((T1 << 24) & 0xff000000);
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rm = ((T0 >> 16) & 0xff) | ((T1 >> 8) & 0xff00)
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| ((T0 >> 8) & 0xff0000) | (T1 & 0xff000000);
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T0 = rd;
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T1 = rm;
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}
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void HELPER(neon_zip_u16)(void)
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{
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uint32_t tmp;
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tmp = (T0 & 0xffff) | (T1 << 16);
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T1 = (T1 & 0xffff0000) | (T0 >> 16);
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T0 = tmp;
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}
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@ -3627,24 +3627,157 @@ static inline void gen_neon_get_scalar(int size, int reg)
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}
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}
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}
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}
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static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
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{
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TCGv rd, rm, tmp;
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rd = new_tmp();
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rm = new_tmp();
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tmp = new_tmp();
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tcg_gen_andi_i32(rd, t0, 0xff);
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tcg_gen_shri_i32(tmp, t0, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t1, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff000000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(rm, t0, 8);
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tcg_gen_andi_i32(rm, rm, 0xff);
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tcg_gen_shri_i32(tmp, t0, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_shli_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_andi_i32(tmp, t1, 0xff000000);
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tcg_gen_or_i32(t1, rm, tmp);
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tcg_gen_mov_i32(t0, rd);
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dead_tmp(tmp);
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dead_tmp(rm);
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dead_tmp(rd);
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}
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static void gen_neon_zip_u8(TCGv t0, TCGv t1)
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{
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TCGv rd, rm, tmp;
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rd = new_tmp();
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rm = new_tmp();
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tmp = new_tmp();
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tcg_gen_andi_i32(rd, t0, 0xff);
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tcg_gen_shli_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t0, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t1, 24);
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tcg_gen_andi_i32(tmp, tmp, 0xff000000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_andi_i32(rm, t1, 0xff000000);
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tcg_gen_shri_i32(tmp, t0, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_shri_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_shri_i32(tmp, t0, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff);
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tcg_gen_or_i32(t1, rm, tmp);
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tcg_gen_mov_i32(t0, rd);
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dead_tmp(tmp);
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dead_tmp(rm);
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dead_tmp(rd);
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}
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static void gen_neon_zip_u16(TCGv t0, TCGv t1)
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{
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TCGv tmp, tmp2;
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tmp = new_tmp();
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tmp2 = new_tmp();
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tcg_gen_andi_i32(tmp, t0, 0xffff);
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tcg_gen_shli_i32(tmp2, t1, 16);
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tcg_gen_or_i32(tmp, tmp, tmp2);
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tcg_gen_andi_i32(t1, t1, 0xffff0000);
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tcg_gen_shri_i32(tmp2, t0, 16);
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tcg_gen_or_i32(t1, t1, tmp2);
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tcg_gen_mov_i32(t0, tmp);
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dead_tmp(tmp2);
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dead_tmp(tmp);
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}
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static void gen_neon_unzip(int reg, int q, int tmp, int size)
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static void gen_neon_unzip(int reg, int q, int tmp, int size)
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{
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{
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int n;
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int n;
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for (n = 0; n < q + 1; n += 2) {
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for (n = 0; n < q + 1; n += 2) {
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NEON_GET_REG(T0, reg, n);
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NEON_GET_REG(T0, reg, n);
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NEON_GET_REG(T0, reg, n + n);
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NEON_GET_REG(T1, reg, n + 1);
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switch (size) {
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switch (size) {
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case 0: gen_helper_neon_unzip_u8(); break;
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case 0: gen_neon_unzip_u8(cpu_T[0], cpu_T[1]); break;
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case 1: gen_helper_neon_zip_u16(); break; /* zip and unzip are the same. */
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case 1: gen_neon_zip_u16(cpu_T[0], cpu_T[1]); break; /* zip and unzip are the same. */
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case 2: /* no-op */; break;
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case 2: /* no-op */; break;
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default: abort();
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default: abort();
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}
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}
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gen_neon_movl_scratch_T0(tmp + n);
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gen_neon_movl_T0_scratch(tmp + n);
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gen_neon_movl_scratch_T1(tmp + n + 1);
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gen_neon_movl_T1_scratch(tmp + n + 1);
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}
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}
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}
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}
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static void gen_neon_trn_u8(TCGv t0, TCGv t1)
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{
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TCGv rd, tmp;
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rd = new_tmp();
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tmp = new_tmp();
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tcg_gen_shli_i32(rd, t0, 8);
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tcg_gen_andi_i32(rd, rd, 0xff00ff00);
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tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 8);
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tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
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tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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dead_tmp(tmp);
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dead_tmp(rd);
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}
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static void gen_neon_trn_u16(TCGv t0, TCGv t1)
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{
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TCGv rd, tmp;
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rd = new_tmp();
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tmp = new_tmp();
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tcg_gen_shli_i32(rd, t0, 16);
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tcg_gen_andi_i32(tmp, t1, 0xffff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 16);
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tcg_gen_andi_i32(tmp, t0, 0xffff0000);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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dead_tmp(tmp);
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dead_tmp(rd);
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}
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static struct {
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static struct {
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int nregs;
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int nregs;
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int interleave;
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int interleave;
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@ -5256,8 +5389,8 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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NEON_GET_REG(T0, rd, n);
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NEON_GET_REG(T0, rd, n);
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NEON_GET_REG(T1, rd, n);
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NEON_GET_REG(T1, rd, n);
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switch (size) {
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switch (size) {
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case 0: gen_helper_neon_zip_u8(); break;
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case 0: gen_neon_zip_u8(cpu_T[0], cpu_T[1]); break;
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case 1: gen_helper_neon_zip_u16(); break;
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case 1: gen_neon_zip_u16(cpu_T[0], cpu_T[1]); break;
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case 2: /* no-op */; break;
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case 2: /* no-op */; break;
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default: abort();
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default: abort();
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}
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}
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@ -5442,8 +5575,8 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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case 33: /* VTRN */
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case 33: /* VTRN */
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NEON_GET_REG(T1, rd, pass);
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NEON_GET_REG(T1, rd, pass);
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switch (size) {
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switch (size) {
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case 0: gen_helper_neon_trn_u8(); break;
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case 0: gen_neon_trn_u8(cpu_T[0], cpu_T[1]); break;
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case 1: gen_helper_neon_trn_u16(); break;
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case 1: gen_neon_trn_u16(cpu_T[0], cpu_T[1]); break;
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case 2: abort();
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case 2: abort();
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default: return 1;
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default: return 1;
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}
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}
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