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target/ppc: Remove msr_le macro

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msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-5-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo 2022-05-04 18:05:23 -03:00 committed by Daniel Henrique Barboza
parent d41ccf6eea
commit 1922322ce4
4 changed files with 11 additions and 11 deletions
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2
target/ppc/cpu.h
View File

@ -355,6 +355,7 @@ typedef enum {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, LE, MSR_LE, 1)
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
@ -486,7 +487,6 @@ FIELD(MSR, PR, MSR_PR, 1)
#define msr_ir ((env->msr >> MSR_IR) & 1)
#define msr_dr ((env->msr >> MSR_DR) & 1)
#define msr_ds ((env->msr >> MSR_DS) & 1)
#define msr_le ((env->msr >> MSR_LE) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)

2
target/ppc/cpu_init.c
View File

@ -7210,7 +7210,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
cpu_synchronize_state(cs);
return !msr_le;
return !FIELD_EX64(env->msr, MSR, LE);
}
#ifdef CONFIG_TCG

2
target/ppc/gdbstub.c
View File

@ -95,7 +95,7 @@ static int ppc_gdb_register_len(int n)
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
{
#ifndef CONFIG_USER_ONLY
if (!msr_le) {
if (!FIELD_EX64(env->msr, MSR, LE)) {
/* do nothing */
} else if (len == 4) {
bswap32s((uint32_t *)mem_buf);

16
target/ppc/mem_helper.c
View File

@ -33,9 +33,9 @@
static inline bool needs_byteswap(const CPUPPCState *env)
{
#if TARGET_BIG_ENDIAN
return msr_le;
return FIELD_EX64(env->msr, MSR, LE);
#else
return !msr_le;
return !FIELD_EX64(env->msr, MSR, LE);
#endif
}
@ -470,8 +470,8 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
#endif
/*
* We use msr_le to determine index ordering in a vector. However,
* byteswapping is not simply controlled by msr_le. We also need to
* We use MSR_LE to determine index ordering in a vector. However,
* byteswapping is not simply controlled by MSR_LE. We also need to
* take into account endianness of the target. This is done for the
* little-endian PPC64 user-mode target.
*/
@ -484,7 +484,7 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
if (msr_le) { \
if (FIELD_EX64(env->msr, MSR, LE)) { \
index = n_elems - index - 1; \
} \
\
@ -511,7 +511,7 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
if (msr_le) { \
if (FIELD_EX64(env->msr, MSR, LE)) { \
index = n_elems - index - 1; \
} \
\
@ -545,7 +545,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
t.s128 = int128_zero(); \
if (nb) { \
nb = (nb >= 16) ? 16 : nb; \
if (msr_le && !lj) { \
if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
for (i = 16; i > 16 - nb; i--) { \
t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
addr = addr_add(env, addr, 1); \
@ -576,7 +576,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
} \
\
nb = (nb >= 16) ? 16 : nb; \
if (msr_le && !lj) { \
if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
for (i = 16; i > 16 - nb; i--) { \
cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
addr = addr_add(env, addr, 1); \