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MIPS queue

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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-2018-06-27' into staging

MIPS queue

# gpg: Signature made Wed 27 Jun 2018 19:16:23 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-2018-06-27:
  target/mips: Fix gdbstub to read/write 64 bit FP registers
  target/mips: Fix data type for offset
  target/mips: Update gen_flt_ldst()
  target/mips: Fix microMIPS on reset
  target/mips: Raise a RI when given fs is n/a from CTC1
  hw/pci-host/xilinx-pcie: don't make "io" region be RAM
  hw/mips/mips_malta: don't make bios region 'nomigrate'
  hw/mips/boston: don't make flash region 'nomigrate'
  MAINTAINERS: update target-mips maintainers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-06-28 14:31:41 +01:00
commit 18896679aa
7 changed files with 28 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -187,7 +187,7 @@ F: disas/microblaze.c
MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
M: Yongbok Kim <yongbok.kim@mips.com>
M: Aleksandar Markovic <aleksandar.markovic@mips.com>
S: Maintained
F: target/mips/
F: hw/mips/
@ -718,7 +718,7 @@ S: Maintained
F: hw/mips/mips_malta.c
Mipssim
M: Yongbok Kim <yongbok.kim@mips.com>
M: Aleksandar Markovic <aleksandar.markovic@mips.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
@ -729,7 +729,7 @@ S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
M: Yongbok Kim <yongbok.kim@mips.com>
M: Aleksandar Markovic <aleksandar.markovic@mips.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c

3
hw/mips/boston.c
View File

@ -471,8 +471,7 @@ static void boston_mach_init(MachineState *machine)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
memory_region_init_rom_nomigrate(flash, NULL,
"boston.flash", 128 * M_BYTE, &err);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
ddr = g_new(MemoryRegion, 1);

2
hw/mips/mips_malta.c
View File

@ -1152,7 +1152,7 @@ void mips_malta_init(MachineState *machine)
* handled by an overlapping region as the resulting ROM code subpage
* regions are not executable.
*/
memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
&error_fatal);
if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
FLASH_ADDRESS, BIOS_SIZE)) {

5
hw/pci-host/xilinx-pcie.c
View File

@ -120,9 +120,8 @@ static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
memory_region_set_enabled(&s->mmio, false);
/* dummy I/O region */
memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
memory_region_set_enabled(&s->io, false);
/* dummy PCI I/O region (not visible to the CPU) */
memory_region_init(&s->io, OBJECT(s), "io", 16);
/* interrupt out */
qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);

3
target/mips/gdbstub.c
View File

@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
default:
if (env->CP0_Status & (1 << CP0St_FR)) {
return gdb_get_regl(mem_buf,
return gdb_get_reg64(mem_buf,
env->active_fpu.fpr[n - 38].d);
} else {
return gdb_get_regl(mem_buf,
@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
default:
if (env->CP0_Status & (1 << CP0St_FR)) {
uint64_t tmp = ldq_p(mem_buf);
env->active_fpu.fpr[n - 38].d = tmp;
} else {
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;

3
target/mips/op_helper.c
View File

@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
break;
default:
if (env->insn_flags & ISA_MIPS32R6) {
do_raise_exception(env, EXCP_RI, GETPC());
}
return;
}
restore_fp_status(env);

28
target/mips/translate.c
View File

@ -2112,7 +2112,7 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7);
#undef OP_ST_ATOMIC
static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
int base, int16_t offset)
int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
@ -2140,7 +2140,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx)
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int16_t offset)
int rt, int base, int offset)
{
TCGv t0, t1, t2;
int mem_idx = ctx->mem_idx;
@ -2337,7 +2337,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
/* Store */
static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
int base, int16_t offset)
int base, int offset)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
int base, int16_t offset)
TCGv t0)
{
TCGv t0 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, base, offset);
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
default:
MIPS_INVAL("flt_ldst");
generate_exception_end(ctx, EXCP_RI);
goto out;
break;
}
out:
tcg_temp_free(t0);
}
static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
int rs, int16_t imm)
{
TCGv t0 = tcg_temp_new();
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (op) {
@ -2497,16 +2494,18 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
check_insn(ctx, ISA_MIPS2);
/* Fallthrough */
default:
gen_flt_ldst(ctx, op, rt, rs, imm);
gen_base_offset_addr(ctx, t0, rs, imm);
gen_flt_ldst(ctx, op, rt, t0);
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
tcg_temp_free(t0);
}
/* Arithmetic with immediate operand */
static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
int rt, int rs, int16_t imm)
int rt, int rs, int imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
@ -20713,6 +20712,11 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
if (env->CP0_Config3 & (1 << CP0C3_ISA)) {
/* microMIPS on reset when Config3.ISA == {1, 3} */
env->hflags |= MIPS_HFLAG_M16;
}
/* MSA */
if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
msa_reset(env);