mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg/tci: Restrict TCG_TARGET_NB_REGS to 16

Browse Source 
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented.  Shortly, we will
rearrange the encoding which will make 32 regs impossible.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-28 14:54:16 -10:00
parent f6ff97ab56
commit 187f44d9da
2 changed files with 5 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
tcg/tci/tcg-target.c.inc
View File

@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5, TCG_REG_R5,
TCG_REG_R6, TCG_REG_R6,
TCG_REG_R7, TCG_REG_R7,
#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8, TCG_REG_R8,
TCG_REG_R9, TCG_REG_R9,
TCG_REG_R10, TCG_REG_R10,
@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13, TCG_REG_R13,
TCG_REG_R14, TCG_REG_R14,
TCG_REG_R15, TCG_REG_R15,
#endif
}; };
#if MAX_OPC_PARAM_IARGS != 6 #if MAX_OPC_PARAM_IARGS != 6
@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = {
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
TCG_REG_R7, TCG_REG_R7,
#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8, TCG_REG_R8,
TCG_REG_R9, TCG_REG_R9,
TCG_REG_R10, TCG_REG_R10,
TCG_REG_R11, TCG_REG_R11,
TCG_REG_R12, TCG_REG_R12,
#else
# error Too few input registers available
#endif
#endif #endif
}; };
@ -245,7 +239,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r05", "r05",
"r06", "r06",
"r07", "r07",
#if TCG_TARGET_NB_REGS >= 16
"r08", "r08",
"r09", "r09",
"r10", "r10",
@ -254,25 +247,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r13", "r13",
"r14", "r14",
"r15", "r15",
#if TCG_TARGET_NB_REGS >= 32
"r16",
"r17",
"r18",
"r19",
"r20",
"r21",
"r22",
"r23",
"r24",
"r25",
"r26",
"r27",
"r28",
"r29",
"r30",
"r31"
#endif
#endif
}; };
#endif #endif

32
tcg/tci/tcg-target.h
View File

@ -133,11 +133,8 @@
#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1
#endif /* TCG_TARGET_REG_BITS == 64 */ #endif /* TCG_TARGET_REG_BITS == 64 */
/* Number of registers available. /* Number of registers available. */
For 32 bit hosts, we need more than 8 registers (call arguments). */
/* #define TCG_TARGET_NB_REGS 8 */
#define TCG_TARGET_NB_REGS 16 #define TCG_TARGET_NB_REGS 16
/* #define TCG_TARGET_NB_REGS 32 */
/* List of registers which are used by TCG. */ /* List of registers which are used by TCG. */
typedef enum { typedef enum {
@ -149,7 +146,6 @@ typedef enum {
TCG_REG_R5, TCG_REG_R5,
TCG_REG_R6, TCG_REG_R6,
TCG_REG_R7, TCG_REG_R7,
#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8, TCG_REG_R8,
TCG_REG_R9, TCG_REG_R9,
TCG_REG_R10, TCG_REG_R10,
@ -158,33 +154,15 @@ typedef enum {
TCG_REG_R13, TCG_REG_R13,
TCG_REG_R14, TCG_REG_R14,
TCG_REG_R15, TCG_REG_R15,
#if TCG_TARGET_NB_REGS >= 32
TCG_REG_R16, TCG_AREG0 = TCG_REG_R14,
TCG_REG_R17, TCG_REG_CALL_STACK = TCG_REG_R15,
TCG_REG_R18,
TCG_REG_R19,
TCG_REG_R20,
TCG_REG_R21,
TCG_REG_R22,
TCG_REG_R23,
TCG_REG_R24,
TCG_REG_R25,
TCG_REG_R26,
TCG_REG_R27,
TCG_REG_R28,
TCG_REG_R29,
TCG_REG_R30,
TCG_REG_R31,
#endif
#endif
/* Special value UINT8_MAX is used by TCI to encode constant values. */ /* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX TCG_CONST = UINT8_MAX
} TCGReg; } TCGReg;
#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
/* Used for function call generation. */ /* Used for function call generation. */
#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
#define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_STACK_ALIGN 16