target/arm: Honor the HCR_EL2.TSW bit
These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -543,6 +543,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TSW. */
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static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -4704,14 +4714,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.access = PL1_W, .type = ARM_CP_NOP },
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{ .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NOP },
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NOP,
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.accessfn = aa64_cacheop_access },
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{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NOP },
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
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.access = PL0_W, .type = ARM_CP_NOP,
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@ -4722,7 +4732,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.accessfn = aa64_cacheop_access },
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{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NOP },
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.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
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/* TLBI operations */
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{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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@ -4903,17 +4913,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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{ .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL1_W },
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{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
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.type = ARM_CP_NOP, .access = PL1_W },
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
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/* MMU Domain access control / MPU write buffer control */
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{ .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
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