target/nios2: Use hw/registerfields.h for CR_TLBMISC fields
Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-30-richard.henderson@linaro.org>
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@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7)
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#define CR_TLBACC_G R_CR_TLBACC_G_MASK
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#define CR_TLBMISC 10
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#define CR_TLBMISC_WAY_SHIFT 20
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#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
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#define CR_TLBMISC_RD (1 << 19)
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#define CR_TLBMISC_WE (1 << 18)
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#define CR_TLBMISC_PID_SHIFT 4
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#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
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#define CR_TLBMISC_DBL (1 << 3)
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#define CR_TLBMISC_BAD (1 << 2)
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#define CR_TLBMISC_PERM (1 << 1)
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#define CR_TLBMISC_D (1 << 0)
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FIELD(CR_TLBMISC, D, 0, 1)
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FIELD(CR_TLBMISC, PERM, 1, 1)
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FIELD(CR_TLBMISC, BAD, 2, 1)
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FIELD(CR_TLBMISC, DBL, 3, 1)
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FIELD(CR_TLBMISC, PID, 4, 14)
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FIELD(CR_TLBMISC, WE, 18, 1)
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FIELD(CR_TLBMISC, RD, 19, 1)
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FIELD(CR_TLBMISC, WAY, 20, 4)
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FIELD(CR_TLBMISC, EE, 24, 1)
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#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK
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#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK
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#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK
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#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK
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#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK
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#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK
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#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK
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#define CR_ENCINJ 11
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#define CR_BADADDR 12
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#define CR_CONFIG 13
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@ -281,11 +281,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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return false;
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}
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if (access_type == MMU_INST_FETCH) {
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env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D;
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} else {
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env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
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}
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env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D,
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access_type != MMU_INST_FETCH);
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env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
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address >> TARGET_PAGE_BITS);
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env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
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@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env,
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target_ulong vaddr, int rw, int mmu_idx)
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{
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Nios2CPU *cpu = env_archcpu(env);
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
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int vpn = vaddr >> 12;
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int way, n_ways = cpu->tlb_num_ways;
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@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) {
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int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
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int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY);
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int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
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int g = FIELD_EX32(v, CR_TLBACC, G);
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int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
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Nios2TLBEntry *entry =
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@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
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entry->data = newData;
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}
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/* Auto-increment tlbmisc.WAY */
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env->ctrl[CR_TLBMISC] =
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(env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
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(((way + 1) & (cpu->tlb_num_ways - 1)) <<
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CR_TLBMISC_WAY_SHIFT);
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env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC],
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CR_TLBMISC, WAY,
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(way + 1) & (cpu->tlb_num_ways - 1));
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}
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/* Writes to TLBACC don't change the read-back value */
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@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
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void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
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{
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Nios2CPU *cpu = env_archcpu(env);
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uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID);
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uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
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uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY);
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trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
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trace_nios2_mmu_write_tlbmisc(way,
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_WE) ? 'W' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_PID_MASK) >> 4);
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new_pid);
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if ((v & CR_TLBMISC_PID_MASK) !=
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
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CR_TLBMISC_PID_SHIFT);
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if (new_pid != old_pid) {
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mmu_flush_pid(env, old_pid);
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}
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/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
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if (v & CR_TLBMISC_RD) {
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int way = (v >> CR_TLBMISC_WAY_SHIFT);
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int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
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env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK;
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env->ctrl[CR_TLBACC] |= entry->data;
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env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
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env->ctrl[CR_TLBMISC] =
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(v & ~CR_TLBMISC_PID_MASK) |
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
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CR_TLBMISC_PID_SHIFT);
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env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID,
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entry->tag &
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((1 << cpu->pid_num_bits) - 1));
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env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR],
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CR_PTEADDR, VPN,
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entry->tag >> TARGET_PAGE_BITS);
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@ -925,7 +925,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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}
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qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
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env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
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FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
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env->mmu.tlbacc_wr);
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#endif
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qemu_fprintf(f, "\n\n");
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