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target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions

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According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Max Chou 2024-03-22 17:25:55 +08:00 committed by Alistair Francis
parent fd53ee268d
commit 17b713c080
1 changed files with 18 additions and 2 deletions
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20
target/riscv/insn_trans/trans_rvv.c.inc
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@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s)
}
}
static bool require_rvfmin(DisasContext *s)
{
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
return false;
}
switch (s->sew) {
case MO_16:
return s->cfg_ptr->ext_zvfhmin;
case MO_32:
return s->cfg_ptr->ext_zve32f;
default:
return false;
}
}
static bool require_scale_rvf(DisasContext *s)
{
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s)
}
switch (s->sew) {
case MO_8:
return s->cfg_ptr->ext_zvfhmin;
case MO_16:
return s->cfg_ptr->ext_zve32f;
case MO_32:
@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}