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target/nios2: Split PC out of env->regs[]

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It is cleaner to have a separate name for this variable.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-17-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:16:47 -07:00
parent 5ea3e9975b
commit 17a406eec5
7 changed files with 58 additions and 65 deletions
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2
linux-user/elfload.c
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@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
(*regs)[30] = -1; /* R_SSTATUS */ (*regs)[30] = -1; /* R_SSTATUS */
(*regs)[31] = tswapreg(env->regs[R_RA]); (*regs)[31] = tswapreg(env->regs[R_RA]);
(*regs)[32] = tswapreg(env->regs[R_PC]); (*regs)[32] = tswapreg(env->pc);
(*regs)[33] = -1; /* R_STATUS */ (*regs)[33] = -1; /* R_STATUS */
(*regs)[34] = tswapreg(env->regs[CR_ESTATUS]); (*regs)[34] = tswapreg(env->regs[CR_ESTATUS]);

19
linux-user/nios2/cpu_loop.c
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@ -43,7 +43,7 @@ void cpu_loop(CPUNios2State *env)
* TODO: This advance should be done in the translator, as * TODO: This advance should be done in the translator, as
* hardware produces an advanced pc as part of all exceptions. * hardware produces an advanced pc as part of all exceptions.
*/ */
env->regs[R_PC] += 4; env->pc += 4;
switch (env->error_code) { switch (env->error_code) {
case 0: case 0:
@ -59,7 +59,7 @@ void cpu_loop(CPUNios2State *env)
break; break;
} }
if (ret == -QEMU_ERESTARTSYS) { if (ret == -QEMU_ERESTARTSYS) {
env->regs[R_PC] -= 4; env->pc -= 4;
break; break;
} }
/* /*
@ -74,22 +74,21 @@ void cpu_loop(CPUNios2State *env)
case 1: case 1:
qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n");
force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); force_sig_fault(TARGET_SIGUSR1, 0, env->pc);
break; break;
case 2: case 2:
qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n");
force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); force_sig_fault(TARGET_SIGUSR2, 0, env->pc);
break; break;
case 31: case 31:
qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n");
/* Match kernel's breakpoint_c(). */ /* Match kernel's breakpoint_c(). */
env->regs[R_PC] -= 4; env->pc -= 4;
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
break; break;
default: default:
qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code);
force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc);
env->regs[R_PC]);
break; break;
case 16: /* QEMU specific, for __kuser_cmpxchg */ case 16: /* QEMU specific, for __kuser_cmpxchg */
@ -120,7 +119,7 @@ void cpu_loop(CPUNios2State *env)
break; break;
case EXCP_DEBUG: case EXCP_DEBUG:
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
break; break;
default: default:
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
@ -156,6 +155,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
env->regs[R_SP] = regs->sp; env->regs[R_SP] = regs->sp;
env->regs[R_GP] = regs->gp; env->regs[R_GP] = regs->gp;
env->regs[CR_ESTATUS] = regs->estatus; env->regs[CR_ESTATUS] = regs->estatus;
env->regs[R_PC] = regs->ea; env->pc = regs->ea;
/* TODO: unsigned long orig_r7; */ /* TODO: unsigned long orig_r7; */
} }

6
linux-user/nios2/signal.c
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@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env)
__put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_RA], &gregs[23]);
__put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_FP], &gregs[24]);
__put_user(env->regs[R_GP], &gregs[25]); __put_user(env->regs[R_GP], &gregs[25]);
__put_user(env->regs[R_PC], &gregs[27]); __put_user(env->pc, &gregs[27]);
__put_user(env->regs[R_SP], &gregs[28]); __put_user(env->regs[R_SP], &gregs[28]);
} }
@ -121,7 +121,7 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc)
__get_user(env->regs[R_GP], &gregs[25]); __get_user(env->regs[R_GP], &gregs[25]);
/* Not really necessary no user settable bits */ /* Not really necessary no user settable bits */
__get_user(temp, &gregs[26]); __get_user(temp, &gregs[26]);
__get_user(env->regs[R_PC], &gregs[27]); __get_user(env->pc, &gregs[27]);
__get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_RA], &gregs[23]);
__get_user(env->regs[R_SP], &gregs[28]); __get_user(env->regs[R_SP], &gregs[28]);
@ -177,7 +177,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
env->regs[4] = sig; env->regs[4] = sig;
env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info); env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info);
env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc); env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc);
env->regs[R_PC] = ka->_sa_handler; env->pc = ka->_sa_handler;
unlock_user_struct(frame, frame_addr, 1); unlock_user_struct(frame, frame_addr, 1);
} }

8
target/nios2/cpu.c
View File

@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
Nios2CPU *cpu = NIOS2_CPU(cs); Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env; CPUNios2State *env = &cpu->env;
env->regs[R_PC] = value; env->pc = value;
} }
static bool nios2_cpu_has_work(CPUState *cs) static bool nios2_cpu_has_work(CPUState *cs)
@ -49,7 +49,7 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev); ncc->parent_reset(dev);
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
env->regs[R_PC] = cpu->reset_addr; env->pc = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */ /* Start in user mode with interrupts enabled. */
@ -156,7 +156,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
if (n < 32) { /* GP regs */ if (n < 32) { /* GP regs */
return gdb_get_reg32(mem_buf, env->regs[n]); return gdb_get_reg32(mem_buf, env->regs[n]);
} else if (n == 32) { /* PC */ } else if (n == 32) { /* PC */
return gdb_get_reg32(mem_buf, env->regs[R_PC]); return gdb_get_reg32(mem_buf, env->pc);
} else if (n < 49) { /* Status regs */ } else if (n < 49) { /* Status regs */
return gdb_get_reg32(mem_buf, env->regs[n - 1]); return gdb_get_reg32(mem_buf, env->regs[n - 1]);
} }
@ -178,7 +178,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (n < 32) { /* GP regs */ if (n < 32) { /* GP regs */
env->regs[n] = ldl_p(mem_buf); env->regs[n] = ldl_p(mem_buf);
} else if (n == 32) { /* PC */ } else if (n == 32) { /* PC */
env->regs[R_PC] = ldl_p(mem_buf); env->pc = ldl_p(mem_buf);
} else if (n < 49) { /* Status regs */ } else if (n < 49) { /* Status regs */
env->regs[n - 1] = ldl_p(mem_buf); env->regs[n - 1] = ldl_p(mem_buf);
} }

10
target/nios2/cpu.h
View File

@ -59,8 +59,8 @@ struct Nios2CPUClass {
#define NUM_GP_REGS 32 #define NUM_GP_REGS 32
#define NUM_CR_REGS 32 #define NUM_CR_REGS 32
/* GP regs + CR regs + PC */ /* GP regs + CR regs */
#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) #define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS)
/* General purpose register aliases */ /* General purpose register aliases */
#define R_ZERO 0 #define R_ZERO 0
@ -130,9 +130,6 @@ struct Nios2CPUClass {
#define CR_MPUBASE (CR_BASE + 14) #define CR_MPUBASE (CR_BASE + 14)
#define CR_MPUACC (CR_BASE + 15) #define CR_MPUACC (CR_BASE + 15)
/* Other registers */
#define R_PC 64
/* Exceptions */ /* Exceptions */
#define EXCP_BREAK 0x1000 #define EXCP_BREAK 0x1000
#define EXCP_RESET 0 #define EXCP_RESET 0
@ -158,6 +155,7 @@ struct Nios2CPUClass {
struct CPUArchState { struct CPUArchState {
uint32_t regs[NUM_CORE_REGS]; uint32_t regs[NUM_CORE_REGS];
uint32_t pc;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
Nios2MMU mmu; Nios2MMU mmu;
@ -237,7 +235,7 @@ typedef Nios2CPU ArchCPU;
static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags) target_ulong *cs_base, uint32_t *flags)
{ {
*pc = env->regs[R_PC]; *pc = env->pc;
*cs_base = 0; *cs_base = 0;
*flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
} }

49
target/nios2/helper.c
View File

@ -38,7 +38,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_IRQ: case EXCP_IRQ:
assert(env->regs[CR_STATUS] & CR_STATUS_PIE); assert(env->regs[CR_STATUS] & CR_STATUS_PIE);
qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->regs[R_PC]); qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[CR_STATUS] |= CR_STATUS_IH; env->regs[CR_STATUS] |= CR_STATUS_IH;
@ -47,14 +47,13 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->regs[R_EA] = env->regs[R_PC] + 4; env->regs[R_EA] = env->pc + 4;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
break; break;
case EXCP_TLBD: case EXCP_TLBD:
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
env->regs[R_PC]);
/* Fast TLB miss */ /* Fast TLB miss */
/* Variation from the spec. Table 3-35 of the cpu reference shows /* Variation from the spec. Table 3-35 of the cpu reference shows
@ -70,11 +69,10 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
env->regs[R_EA] = env->regs[R_PC] + 4; env->regs[R_EA] = env->pc + 4;
env->regs[R_PC] = cpu->fast_tlb_miss_addr; env->pc = cpu->fast_tlb_miss_addr;
} else { } else {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
env->regs[R_PC]);
/* Double TLB miss */ /* Double TLB miss */
env->regs[CR_STATUS] |= CR_STATUS_EH; env->regs[CR_STATUS] |= CR_STATUS_EH;
@ -85,14 +83,14 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL; env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
} }
break; break;
case EXCP_TLBR: case EXCP_TLBR:
case EXCP_TLBW: case EXCP_TLBW:
case EXCP_TLBX: case EXCP_TLBX:
qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->regs[R_PC]); qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[CR_STATUS] |= CR_STATUS_EH; env->regs[CR_STATUS] |= CR_STATUS_EH;
@ -105,19 +103,18 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
} }
env->regs[R_EA] = env->regs[R_PC] + 4; env->regs[R_EA] = env->pc + 4;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
break; break;
case EXCP_SUPERA: case EXCP_SUPERA:
case EXCP_SUPERI: case EXCP_SUPERI:
case EXCP_SUPERD: case EXCP_SUPERD:
qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
env->regs[R_PC]);
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[R_EA] = env->regs[R_PC] + 4; env->regs[R_EA] = env->pc + 4;
} }
env->regs[CR_STATUS] |= CR_STATUS_EH; env->regs[CR_STATUS] |= CR_STATUS_EH;
@ -126,17 +123,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
break; break;
case EXCP_ILLEGAL: case EXCP_ILLEGAL:
case EXCP_TRAP: case EXCP_TRAP:
qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
env->regs[R_PC]);
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[R_EA] = env->regs[R_PC] + 4; env->regs[R_EA] = env->pc + 4;
} }
env->regs[CR_STATUS] |= CR_STATUS_EH; env->regs[CR_STATUS] |= CR_STATUS_EH;
@ -145,24 +141,23 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
break; break;
case EXCP_BREAK: case EXCP_BREAK:
qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
env->regs[R_PC]);
/* The semihosting instruction is "break 1". */ /* The semihosting instruction is "break 1". */
if (semihosting_enabled() && if (semihosting_enabled() &&
cpu_ldl_code(env, env->regs[R_PC]) == 0x003da07a) { cpu_ldl_code(env, env->pc) == 0x003da07a) {
qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n");
env->regs[R_PC] += 4; env->pc += 4;
do_nios2_semihosting(env); do_nios2_semihosting(env);
break; break;
} }
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_BSTATUS] = env->regs[CR_STATUS]; env->regs[CR_BSTATUS] = env->regs[CR_STATUS];
env->regs[R_BA] = env->regs[R_PC] + 4; env->regs[R_BA] = env->pc + 4;
} }
env->regs[CR_STATUS] |= CR_STATUS_EH; env->regs[CR_STATUS] |= CR_STATUS_EH;
@ -171,7 +166,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->regs[R_PC] = cpu->exception_addr; env->pc = cpu->exception_addr;
break; break;
default: default:

29
target/nios2/translate.c
View File

@ -104,6 +104,7 @@ typedef struct DisasContext {
} DisasContext; } DisasContext;
static TCGv cpu_R[NUM_CORE_REGS]; static TCGv cpu_R[NUM_CORE_REGS];
static TCGv cpu_pc;
typedef struct Nios2Instruction { typedef struct Nios2Instruction {
void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags);
@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc,
{ {
TCGv_i32 tmp = tcg_const_i32(index); TCGv_i32 tmp = tcg_const_i32(index);
tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_helper_raise_exception(cpu_env, tmp); gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
if (translator_use_goto_tb(&dc->base, dest)) { if (translator_use_goto_tb(&dc->base, dest)) {
tcg_gen_goto_tb(n); tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_R[R_PC], dest); tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(tb, n); tcg_gen_exit_tb(tb, n);
} else { } else {
tcg_gen_movi_tl(cpu_R[R_PC], dest); tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
} }
} }
@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
} }
tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]);
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
} }
@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ra */ /* PC <- ra */
static void ret(DisasContext *dc, uint32_t code, uint32_t flags) static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]);
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
} }
@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ba */ /* PC <- ba */
static void bret(DisasContext *dc, uint32_t code, uint32_t flags) static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]);
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
} }
@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
R_TYPE(instr, code); R_TYPE(instr, code);
tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
} }
@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
R_TYPE(instr, code); R_TYPE(instr, code);
tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
@ -742,7 +743,7 @@ illegal_op:
t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
} }
static const char * const regnames[] = { static const char * const regnames[NUM_CORE_REGS] = {
"zero", "at", "r2", "r3", "zero", "at", "r2", "r3",
"r4", "r5", "r6", "r7", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r8", "r9", "r10", "r11",
@ -759,7 +760,6 @@ static const char * const regnames[] = {
"reserved6", "reserved7", "reserved8", "reserved9", "reserved6", "reserved7", "reserved8", "reserved9",
"reserved10", "reserved11", "reserved12", "reserved13", "reserved10", "reserved11", "reserved12", "reserved13",
"reserved14", "reserved15", "reserved16", "reserved17", "reserved14", "reserved15", "reserved16", "reserved17",
"rpc"
}; };
#include "exec/gen-icount.h" #include "exec/gen-icount.h"
@ -827,7 +827,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
case DISAS_UPDATE: case DISAS_UPDATE:
/* Save the current PC back into the CPU register */ /* Save the current PC back into the CPU register */
tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
break; break;
@ -877,8 +877,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
return; return;
} }
qemu_fprintf(f, "IN: PC=%x %s\n", qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc));
env->regs[R_PC], lookup_symbol(env->regs[R_PC]));
for (i = 0; i < NUM_CORE_REGS; i++) { for (i = 0; i < NUM_CORE_REGS; i++) {
qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]); qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]);
@ -904,10 +903,12 @@ void nios2_tcg_init(void)
offsetof(CPUNios2State, regs[i]), offsetof(CPUNios2State, regs[i]),
regnames[i]); regnames[i]);
} }
cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, pc), "pc");
} }
void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb, void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb,
target_ulong *data) target_ulong *data)
{ {
env->regs[R_PC] = data[0]; env->pc = data[0];
} }