target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
While dozens of files include "cpu.h", only 3 files require these NVIC helper declarations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230206223502.25122-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
Peter Maydell
parent
8f4e07c9d1
commit
165876f22c
@ -83,4 +83,127 @@ struct NVICState {
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qemu_irq sysresetreq;
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};
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/* Interface between CPU and Interrupt controller. */
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/**
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* armv7m_nvic_set_pending: mark the specified exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Marks the specified exception as pending. Note that we will assert()
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* if @secure is true and @irq does not specify one of the fixed set
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* of architecturally banked exceptions.
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*/
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void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_set_pending_derived: mark this derived exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Similar to armv7m_nvic_set_pending(), but specifically for derived
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* exceptions (exceptions generated in the course of trying to take
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* a different exception).
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*/
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void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Similar to armv7m_nvic_set_pending(), but specifically for exceptions
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* generated in the course of lazy stacking of FP registers.
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*/
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void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_get_pending_irq_info: return highest priority pending
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* exception, and whether it targets Secure state
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* @s: the NVIC
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* @pirq: set to pending exception number
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* @ptargets_secure: set to whether pending exception targets Secure
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*
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* This function writes the number of the highest priority pending
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* exception (the one which would be made active by
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* armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
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* to true if the current highest priority pending exception should
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* be taken to Secure state, false for NS.
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*/
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void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
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bool *ptargets_secure);
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/**
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* armv7m_nvic_acknowledge_irq: make highest priority pending exception active
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* @s: the NVIC
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*
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* Move the current highest priority pending exception from the pending
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* state to the active state, and update v7m.exception to indicate that
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* it is the exception currently being handled.
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*/
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void armv7m_nvic_acknowledge_irq(NVICState *s);
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/**
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* armv7m_nvic_complete_irq: complete specified interrupt or exception
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* @s: the NVIC
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* @irq: the exception number to complete
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* @secure: true if this exception was secure
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*
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* Returns: -1 if the irq was not active
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* 1 if completing this irq brought us back to base (no active irqs)
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* 0 if there is still an irq active after this one was completed
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* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
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*/
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int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Return whether an exception is "ready", i.e. whether the exception is
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* enabled and is configured at a priority which would allow it to
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* interrupt the current execution priority. This controls whether the
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* RDY bit for it in the FPCCR is set.
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*/
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bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_raw_execution_priority: return the raw execution priority
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* @s: the NVIC
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*
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* Returns: the raw execution priority as defined by the v8M architecture.
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* This is the execution priority minus the effects of AIRCR.PRIS,
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* and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
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* (v8M ARM ARM I_PKLD.)
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*/
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int armv7m_nvic_raw_execution_priority(NVICState *s);
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/**
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* armv7m_nvic_neg_prio_requested: return true if the requested execution
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* priority is negative for the specified security state.
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* @s: the NVIC
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* @secure: the security state to test
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* This corresponds to the pseudocode IsReqExecPriNeg().
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*/
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#ifndef CONFIG_USER_ONLY
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bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
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#else
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static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
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{
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return false;
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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bool armv7m_nvic_can_take_pending_exception(NVICState *s);
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#else
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static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
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{
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return true;
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}
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#endif
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#endif
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@ -36,8 +36,10 @@
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#include "hw/boards.h"
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#ifdef CONFIG_TCG
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#include "hw/intc/armv7m_nvic.h"
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#endif
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#endif /* CONFIG_TCG */
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#endif /* !CONFIG_USER_ONLY */
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#include "sysemu/tcg.h"
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#include "sysemu/qtest.h"
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#include "sysemu/hw_accel.h"
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123
target/arm/cpu.h
123
target/arm/cpu.h
@ -2559,129 +2559,6 @@ void arm_cpu_list(void);
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uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
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uint32_t cur_el, bool secure);
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/* Interface between CPU and Interrupt controller. */
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#ifndef CONFIG_USER_ONLY
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bool armv7m_nvic_can_take_pending_exception(NVICState *s);
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#else
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static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
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{
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return true;
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}
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#endif
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/**
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* armv7m_nvic_set_pending: mark the specified exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Marks the specified exception as pending. Note that we will assert()
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* if @secure is true and @irq does not specify one of the fixed set
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* of architecturally banked exceptions.
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*/
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void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_set_pending_derived: mark this derived exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Similar to armv7m_nvic_set_pending(), but specifically for derived
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* exceptions (exceptions generated in the course of trying to take
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* a different exception).
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*/
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void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Similar to armv7m_nvic_set_pending(), but specifically for exceptions
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* generated in the course of lazy stacking of FP registers.
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*/
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void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_get_pending_irq_info: return highest priority pending
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* exception, and whether it targets Secure state
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* @s: the NVIC
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* @pirq: set to pending exception number
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* @ptargets_secure: set to whether pending exception targets Secure
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*
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* This function writes the number of the highest priority pending
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* exception (the one which would be made active by
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* armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
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* to true if the current highest priority pending exception should
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* be taken to Secure state, false for NS.
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*/
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void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
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bool *ptargets_secure);
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/**
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* armv7m_nvic_acknowledge_irq: make highest priority pending exception active
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* @s: the NVIC
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*
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* Move the current highest priority pending exception from the pending
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* state to the active state, and update v7m.exception to indicate that
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* it is the exception currently being handled.
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*/
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void armv7m_nvic_acknowledge_irq(NVICState *s);
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/**
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* armv7m_nvic_complete_irq: complete specified interrupt or exception
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* @s: the NVIC
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* @irq: the exception number to complete
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* @secure: true if this exception was secure
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*
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* Returns: -1 if the irq was not active
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* 1 if completing this irq brought us back to base (no active irqs)
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* 0 if there is still an irq active after this one was completed
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* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
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*/
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int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
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* @s: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Return whether an exception is "ready", i.e. whether the exception is
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* enabled and is configured at a priority which would allow it to
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* interrupt the current execution priority. This controls whether the
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* RDY bit for it in the FPCCR is set.
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*/
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bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
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/**
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* armv7m_nvic_raw_execution_priority: return the raw execution priority
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* @s: the NVIC
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*
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* Returns: the raw execution priority as defined by the v8M architecture.
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* This is the execution priority minus the effects of AIRCR.PRIS,
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* and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
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* (v8M ARM ARM I_PKLD.)
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*/
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int armv7m_nvic_raw_execution_priority(NVICState *s);
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/**
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* armv7m_nvic_neg_prio_requested: return true if the requested execution
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* priority is negative for the specified security state.
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* @s: the NVIC
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* @secure: the security state to test
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* This corresponds to the pseudocode IsReqExecPriNeg().
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*/
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#ifndef CONFIG_USER_ONLY
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bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
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#else
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static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
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{
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return false;
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}
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#endif
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/* Interface for defining coprocessor registers.
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* Registers are defined in tables of arm_cp_reginfo structs
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* which are passed to define_arm_cp_regs().
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@ -19,6 +19,9 @@
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#include "hw/boards.h"
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#endif
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#include "cpregs.h"
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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#include "hw/intc/armv7m_nvic.h"
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#endif
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/* Share AArch32 -cpu max features with AArch64. */
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@ -18,6 +18,9 @@
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#include "exec/cpu_ldst.h"
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#include "semihosting/common-semi.h"
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/intc/armv7m_nvic.h"
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#endif
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static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
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uint32_t reg, uint32_t val)
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