arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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TCGv_i32 tcg_rmode = NULL;
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TCGv_ptr tcg_fpstatus = NULL;
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bool need_rmode = false;
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bool need_fpst = true;
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int rmode;
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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need_rmode = true;
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rmode = FPROUNDING_ZERO;
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break;
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case 0x2f: /* FABS */
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case 0x6f: /* FNEG */
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need_fpst = false;
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break;
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default:
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fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
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g_assert_not_reached();
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@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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return;
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}
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if (need_rmode) {
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if (need_rmode || need_fpst) {
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tcg_fpstatus = get_fpstatus_ptr(true);
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}
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@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x7b: /* FCVTZU */
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gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x6f: /* FNEG */
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tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
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break;
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default:
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g_assert_not_reached();
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}
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@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x59: /* FRINTX */
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gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x2f: /* FABS */
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tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
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break;
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case 0x6f: /* FNEG */
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tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
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break;
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default:
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g_assert_not_reached();
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}
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