mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw/arm/smmuv3: add support for stage 1 access fault

Browse Source 
An access fault is raised when the Access Flag is not set in the
looked-up PTE and the AFFD field is not set in the corresponding context
descriptor. This was already implemented for stage 2. Implement it for
stage 1 as well.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Mostafa Saleh <smostafa@google.com>
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
[PMM: tweaked comment text]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2024-02-13 09:22:11 +01:00 committed by Peter Maydell
parent bfe30b02e7
commit 15f6c16e6e
4 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
hw/arm/smmu-common.c
View File

@ -364,6 +364,17 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
pte_addr, pte, iova, gpa, pte_addr, pte, iova, gpa,
block_size >> 20); block_size >> 20);
} }
/*
* QEMU does not currently implement HTTU, so if AFFD and PTE.AF
* are 0 we take an Access flag fault. (5.4. Context Descriptor)
* An Access flag fault takes priority over a Permission fault.
*/
if (!PTE_AF(pte) && !cfg->affd) {
info->type = SMMU_PTW_ERR_ACCESS;
goto error;
}
ap = PTE_AP(pte); ap = PTE_AP(pte);
if (is_permission_fault(ap, perm)) { if (is_permission_fault(ap, perm)) {
info->type = SMMU_PTW_ERR_PERMISSION; info->type = SMMU_PTW_ERR_PERMISSION;

1
hw/arm/smmuv3-internal.h
View File

@ -624,6 +624,7 @@ static inline int pa_range(STE *ste)
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
#define CD_ENDI(x) extract32((x)->word[0], 15, 1) #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
#define CD_IPS(x) extract32((x)->word[1], 0 , 3) #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
#define CD_TBI(x) extract32((x)->word[1], 6 , 2) #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
#define CD_HD(x) extract32((x)->word[1], 10 , 1) #define CD_HD(x) extract32((x)->word[1], 10 , 1)
#define CD_HA(x) extract32((x)->word[1], 11 , 1) #define CD_HA(x) extract32((x)->word[1], 11 , 1)

1
hw/arm/smmuv3.c
View File

@ -684,6 +684,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
cfg->tbi = CD_TBI(cd); cfg->tbi = CD_TBI(cd);
cfg->asid = CD_ASID(cd); cfg->asid = CD_ASID(cd);
cfg->affd = CD_AFFD(cd);
trace_smmuv3_decode_cd(cfg->oas); trace_smmuv3_decode_cd(cfg->oas);

1
include/hw/arm/smmu-common.h
View File

@ -92,6 +92,7 @@ typedef struct SMMUTransCfg {
bool disabled; /* smmu is disabled */ bool disabled; /* smmu is disabled */
bool bypassed; /* translation is bypassed */ bool bypassed; /* translation is bypassed */
bool aborted; /* translation is aborted */ bool aborted; /* translation is aborted */
bool affd; /* AF fault disable */
uint32_t iotlb_hits; /* counts IOTLB hits */ uint32_t iotlb_hits; /* counts IOTLB hits */
uint32_t iotlb_misses; /* counts IOTLB misses*/ uint32_t iotlb_misses; /* counts IOTLB misses*/
/* Used by stage-1 only. */ /* Used by stage-1 only. */