MIPS patches queue
- Fine-grained MAINTAINERS sections - Fix MSA MADDV.B / MSUBV.B opcodes - Convert MSA opcodes to decodetree - Correct Loongson-3A4000 MSAIR register - Do not accept ELF nanoMIPS binaries on linux-user - Use ISA instead of PCI interrupts in VT82C686 PCI device -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmGBP/AACgkQ4+MsLN6t wN71pxAAlzPE8VVJAWP7TLL/Y+j4LhmHZwdkJMyZ1YhHg9loOOzbH+Pm9vgwHzjp O50I+e25LlJfmhR0/UA5nPSGDGQn6yK9bzB31R4ClQaMqyThDysA7HAJnnPQyUOF 9COxd3QdfALn0+0N/Y8uVe8opMAy+pi9G0hIp84ngEXFFph3XZ8GFfdg+ThxhYGG ERQoNqkQpAxWg6Bh1iBH036z6FH8BzFM4Ja6Bm2cjrzLm2PbwOAeFDHJ//961TPK GLTicX3J0xO80X73lF5ipCpyQvo+vCgw/tbSv/I0XS3skMhTHEjucWVBZQ1Awu8e +cK9rRmXMywakMryMUC5C2/8CRNN6FznJYWbnL4TpifqFZ1gmlStKQoHKNKAmrr/ h/plPbyugP2ELdH2gwfjF3uf13Cww2E0vsRJSBuBhSFwb+FEppFUQLykWji2BgyO azB2k3bp6sdLTPhpIWWu1Aq/V3cOq0p2zJip6bS0k8TTQV3q2lLMNc8BF5O0J7Jh KHb6hhqKkEAQhYksyOEsEf+5BtFhiDIfOI3ORu9Zz+L3ffzZlXZjCYgsGsNnGGz1 syoLvrVcdXq7qA4qeocZJ+RSpvvkXpZt0pVBJaw4fenH5XED7GxaQGx9GjhC1UQa VC7mI3D2DUBJACPeUecCJ1MdJfCkAenT5y1bm/w6vqYEF8nLhDE= =XMNZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging MIPS patches queue - Fine-grained MAINTAINERS sections - Fix MSA MADDV.B / MSUBV.B opcodes - Convert MSA opcodes to decodetree - Correct Loongson-3A4000 MSAIR register - Do not accept ELF nanoMIPS binaries on linux-user - Use ISA instead of PCI interrupts in VT82C686 PCI device # gpg: Signature made Tue 02 Nov 2021 09:41:04 AM EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * remotes/philmd/tags/mips-20211102: (41 commits) Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts usb/uhci: Replace pci_set_irq with qemu_set_irq usb/uhci: Disallow user creating a vt82c686-uhci-pci device usb/uhci: Misc clean up target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU target/mips: Fix Loongson-3A4000 MSAIR config register target/mips: Remove one MSA unnecessary decodetree overlap group target/mips: Remove generic MSA opcode target/mips: Convert CTCMSA opcode to decodetree target/mips: Convert CFCMSA opcode to decodetree target/mips: Convert MSA MOVE.V opcode to decodetree target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree target/mips: Convert MSA COPY_U opcode to decodetree target/mips: Convert MSA ELM instruction format to decodetree target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
commit
157f75435e
37
MAINTAINERS
37
MAINTAINERS
@ -109,6 +109,12 @@ K: ^Subject:.*(?i)s390x?
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|||||||
T: git https://gitlab.com/cohuck/qemu.git s390-next
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T: git https://gitlab.com/cohuck/qemu.git s390-next
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||||||
L: qemu-s390x@nongnu.org
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L: qemu-s390x@nongnu.org
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||||||
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|
MIPS general architecture support
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||||||
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M: Philippe Mathieu-Daudé <f4bug@amsat.org>
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||||||
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R: Jiaxun Yang <jiaxun.yang@flygoat.com>
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||||||
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S: Odd Fixes
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||||||
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K: ^Subject:.*(?i)mips
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||||||
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Guest CPU cores (TCG)
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Guest CPU cores (TCG)
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||||||
---------------------
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---------------------
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Overall TCG CPUs
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Overall TCG CPUs
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||||||
@ -230,19 +236,9 @@ R: Jiaxun Yang <jiaxun.yang@flygoat.com>
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|||||||
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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||||||
S: Odd Fixes
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S: Odd Fixes
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||||||
F: target/mips/
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F: target/mips/
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F: configs/devices/mips*/*
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F: disas/mips.c
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F: disas/mips.c
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||||||
F: docs/system/cpu-models-mips.rst.inc
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F: docs/system/cpu-models-mips.rst.inc
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F: hw/intc/mips_gic.c
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F: hw/mips/
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F: hw/misc/mips_*
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F: hw/timer/mips_gictimer.c
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F: include/hw/intc/mips_gic.h
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F: include/hw/mips/
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F: include/hw/misc/mips_*
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F: include/hw/timer/mips_gictimer.h
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F: tests/tcg/mips/
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F: tests/tcg/mips/
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||||||
K: ^Subject:.*(?i)mips
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|
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MIPS TCG CPUs (nanoMIPS ISA)
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MIPS TCG CPUs (nanoMIPS ISA)
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S: Orphan
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S: Orphan
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@ -1170,6 +1166,13 @@ F: hw/microblaze/petalogix_ml605_mmu.c
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|||||||
|
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||||||
MIPS Machines
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MIPS Machines
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||||||
-------------
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-------------
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||||||
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Overall MIPS Machines
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||||||
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M: Philippe Mathieu-Daudé <f4bug@amsat.org>
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||||||
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S: Odd Fixes
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||||||
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F: configs/devices/mips*/*
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||||||
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F: hw/mips/
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F: include/hw/mips/
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Jazz
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Jazz
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||||||
M: Hervé Poussineau <hpoussin@reactos.org>
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M: Hervé Poussineau <hpoussin@reactos.org>
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||||||
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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@ -2267,6 +2270,20 @@ S: Odd Fixes
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|||||||
F: hw/intc/openpic.c
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F: hw/intc/openpic.c
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F: include/hw/ppc/openpic.h
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F: include/hw/ppc/openpic.h
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|
MIPS CPS
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||||||
|
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
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||||||
|
S: Odd Fixes
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||||||
|
F: hw/misc/mips_*
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||||||
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F: include/hw/misc/mips_*
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|
||||||
|
MIPS GIC
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||||||
|
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
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||||||
|
S: Odd Fixes
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||||||
|
F: hw/intc/mips_gic.c
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F: hw/timer/mips_gictimer.c
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F: include/hw/intc/mips_gic.h
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F: include/hw/timer/mips_gictimer.h
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||||||
|
|
||||||
Subsystems
|
Subsystems
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||||||
----------
|
----------
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Overall Audio backends
|
Overall Audio backends
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@ -31,6 +31,7 @@
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#include "hw/usb/uhci-regs.h"
|
#include "hw/usb/uhci-regs.h"
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#include "migration/vmstate.h"
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#include "migration/vmstate.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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|
#include "hw/irq.h"
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#include "hw/qdev-properties.h"
|
#include "hw/qdev-properties.h"
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#include "qapi/error.h"
|
#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/timer.h"
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@ -290,7 +291,7 @@ static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
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|
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||||||
static void uhci_update_irq(UHCIState *s)
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static void uhci_update_irq(UHCIState *s)
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{
|
{
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int level;
|
int level = 0;
|
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if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
|
if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
|
||||||
((s->status2 & 2) && (s->intr & (1 << 3))) ||
|
((s->status2 & 2) && (s->intr & (1 << 3))) ||
|
||||||
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
|
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
|
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@ -298,10 +299,8 @@ static void uhci_update_irq(UHCIState *s)
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(s->status & UHCI_STS_HSERR) ||
|
(s->status & UHCI_STS_HSERR) ||
|
||||||
(s->status & UHCI_STS_HCPERR)) {
|
(s->status & UHCI_STS_HCPERR)) {
|
||||||
level = 1;
|
level = 1;
|
||||||
} else {
|
|
||||||
level = 0;
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|
||||||
}
|
}
|
||||||
pci_set_irq(&s->dev, level);
|
qemu_set_irq(s->irq, level);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uhci_reset(DeviceState *dev)
|
static void uhci_reset(DeviceState *dev)
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||||||
@ -1170,9 +1169,9 @@ void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
|
|||||||
|
|
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pci_conf[PCI_CLASS_PROG] = 0x00;
|
pci_conf[PCI_CLASS_PROG] = 0x00;
|
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/* TODO: reset value should be 0. */
|
/* TODO: reset value should be 0. */
|
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pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
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pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */
|
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|
|
||||||
pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
|
pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
|
||||||
|
s->irq = pci_allocate_irq(dev);
|
||||||
|
|
||||||
if (s->masterbus) {
|
if (s->masterbus) {
|
||||||
USBPort *ports[NB_PORTS];
|
USBPort *ports[NB_PORTS];
|
||||||
@ -1285,6 +1284,9 @@ void uhci_data_class_init(ObjectClass *klass, void *data)
|
|||||||
} else {
|
} else {
|
||||||
device_class_set_props(dc, uhci_properties_standalone);
|
device_class_set_props(dc, uhci_properties_standalone);
|
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}
|
}
|
||||||
|
if (info->notuser) {
|
||||||
|
dc->user_creatable = false;
|
||||||
|
}
|
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u->info = *info;
|
u->info = *info;
|
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}
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}
|
||||||
|
|
||||||
|
@ -60,7 +60,7 @@ typedef struct UHCIState {
|
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uint32_t frame_bandwidth;
|
uint32_t frame_bandwidth;
|
||||||
bool completions_only;
|
bool completions_only;
|
||||||
UHCIPort ports[NB_PORTS];
|
UHCIPort ports[NB_PORTS];
|
||||||
|
qemu_irq irq;
|
||||||
/* Interrupts that should be raised at the end of the current frame. */
|
/* Interrupts that should be raised at the end of the current frame. */
|
||||||
uint32_t pending_int_mask;
|
uint32_t pending_int_mask;
|
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|
|
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@ -85,6 +85,7 @@ typedef struct UHCIInfo {
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uint8_t irq_pin;
|
uint8_t irq_pin;
|
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void (*realize)(PCIDevice *dev, Error **errp);
|
void (*realize)(PCIDevice *dev, Error **errp);
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bool unplug;
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bool unplug;
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bool notuser; /* disallow user_creatable */
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} UHCIInfo;
|
} UHCIInfo;
|
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|
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void uhci_data_class_init(ObjectClass *klass, void *data);
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void uhci_data_class_init(ObjectClass *klass, void *data);
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@ -1,6 +1,17 @@
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#include "qemu/osdep.h"
|
#include "qemu/osdep.h"
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#include "hw/irq.h"
|
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|
#include "hw/isa/vt82c686.h"
|
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#include "hcd-uhci.h"
|
#include "hcd-uhci.h"
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|
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static void uhci_isa_set_irq(void *opaque, int irq_num, int level)
|
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|
{
|
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UHCIState *s = opaque;
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|
uint8_t irq = pci_get_byte(s->dev.config + PCI_INTERRUPT_LINE);
|
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|
if (irq > 0 && irq < 15) {
|
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|
via_isa_set_irq(pci_get_function_0(&s->dev), irq, level);
|
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|
}
|
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|
}
|
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|
|
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static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
|
static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
|
||||||
{
|
{
|
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UHCIState *s = UHCI(dev);
|
UHCIState *s = UHCI(dev);
|
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@ -14,6 +25,8 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
|
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pci_set_long(pci_conf + 0xc0, 0x00002000);
|
pci_set_long(pci_conf + 0xc0, 0x00002000);
|
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|
|
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usb_uhci_common_realize(dev, errp);
|
usb_uhci_common_realize(dev, errp);
|
||||||
|
object_unref(s->irq);
|
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|
s->irq = qemu_allocate_irq(uhci_isa_set_irq, s, 0);
|
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}
|
}
|
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|
|
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static UHCIInfo uhci_info[] = {
|
static UHCIInfo uhci_info[] = {
|
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@ -25,6 +38,8 @@ static UHCIInfo uhci_info[] = {
|
|||||||
.irq_pin = 3,
|
.irq_pin = 3,
|
||||||
.realize = usb_uhci_vt82c686b_realize,
|
.realize = usb_uhci_vt82c686b_realize,
|
||||||
.unplug = true,
|
.unplug = true,
|
||||||
|
/* Reason: only works as USB function of VT82xx superio chips */
|
||||||
|
.notuser = true,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -925,8 +925,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
|
|||||||
#endif
|
#endif
|
||||||
#define ELF_ARCH EM_MIPS
|
#define ELF_ARCH EM_MIPS
|
||||||
|
|
||||||
#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_NANOMIPS)
|
|
||||||
|
|
||||||
#ifdef TARGET_ABI_MIPSN32
|
#ifdef TARGET_ABI_MIPSN32
|
||||||
#define elf_check_abi(x) ((x) & EF_MIPS_ABI2)
|
#define elf_check_abi(x) ((x) & EF_MIPS_ABI2)
|
||||||
#else
|
#else
|
||||||
|
@ -369,7 +369,6 @@ const mips_def_t mips_defs[] =
|
|||||||
* Config3: VZ, CTXTC, CDMM, TL
|
* Config3: VZ, CTXTC, CDMM, TL
|
||||||
* Config4: MMUExtDef
|
* Config4: MMUExtDef
|
||||||
* Config5: MRP
|
* Config5: MRP
|
||||||
* FIR(FCR0): Has2008
|
|
||||||
* */
|
* */
|
||||||
.name = "P5600",
|
.name = "P5600",
|
||||||
.CP0_PRid = 0x0001A800,
|
.CP0_PRid = 0x0001A800,
|
||||||
@ -886,6 +885,7 @@ const mips_def_t mips_defs[] =
|
|||||||
(0x1 << FCR0_D) | (0x1 << FCR0_S),
|
(0x1 << FCR0_D) | (0x1 << FCR0_S),
|
||||||
.CP1_fcr31 = 0,
|
.CP1_fcr31 = 0,
|
||||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||||
|
.MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
|
||||||
.SEGBITS = 48,
|
.SEGBITS = 48,
|
||||||
.PABITS = 48,
|
.PABITS = 48,
|
||||||
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
|
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
|
||||||
|
@ -13,19 +13,246 @@
|
|||||||
|
|
||||||
&r rs rt rd sa
|
&r rs rt rd sa
|
||||||
|
|
||||||
&msa_bz df wt s16
|
&msa_r df wd ws wt
|
||||||
|
&msa_bz df wt sa
|
||||||
|
&msa_ldi df wd sa
|
||||||
|
&msa_i df wd ws sa
|
||||||
|
&msa_bit df wd ws m
|
||||||
|
&msa_elm_df df wd ws n
|
||||||
|
&msa_elm wd ws
|
||||||
|
|
||||||
|
%elm_df 16:6 !function=elm_df
|
||||||
|
%elm_n 16:6 !function=elm_n
|
||||||
|
%bit_df 16:7 !function=bit_df
|
||||||
|
%bit_m 16:7 !function=bit_m
|
||||||
|
%2r_df_w 16:1 !function=plus_2
|
||||||
|
%3r_df_h 21:1 !function=plus_1
|
||||||
|
%3r_df_w 21:1 !function=plus_2
|
||||||
|
|
||||||
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
|
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
|
||||||
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
|
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
|
||||||
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
|
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
|
||||||
|
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
|
||||||
|
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
|
||||||
|
@elm ...... .......... ws:5 wd:5 ...... &msa_elm
|
||||||
|
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
|
||||||
|
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
|
||||||
|
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
|
||||||
|
@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
|
||||||
|
@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
|
||||||
|
@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
|
||||||
|
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
|
||||||
|
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
|
||||||
|
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
|
||||||
|
@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i df=0
|
||||||
|
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
|
||||||
|
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m
|
||||||
|
|
||||||
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
|
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
|
||||||
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
|
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
|
||||||
|
|
||||||
BZ_V 010001 01011 ..... ................ @bz
|
BZ_V 010001 01011 ..... ................ @bz_v
|
||||||
BNZ_V 010001 01111 ..... ................ @bz
|
BNZ_V 010001 01111 ..... ................ @bz_v
|
||||||
|
BZ 010001 110 .. ..... ................ @bz
|
||||||
|
BNZ 010001 111 .. ..... ................ @bz
|
||||||
|
|
||||||
BZ_x 010001 110 .. ..... ................ @bz_df
|
ANDI 011110 00 ........ ..... ..... 000000 @i8
|
||||||
BNZ_x 010001 111 .. ..... ................ @bz_df
|
ORI 011110 01 ........ ..... ..... 000000 @i8
|
||||||
|
NORI 011110 10 ........ ..... ..... 000000 @i8
|
||||||
|
XORI 011110 11 ........ ..... ..... 000000 @i8
|
||||||
|
BMNZI 011110 00 ........ ..... ..... 000001 @i8
|
||||||
|
BMZI 011110 01 ........ ..... ..... 000001 @i8
|
||||||
|
BSELI 011110 10 ........ ..... ..... 000001 @i8
|
||||||
|
SHF 011110 .. ........ ..... ..... 000010 @i8_df
|
||||||
|
|
||||||
MSA 011110 --------------------------
|
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
|
||||||
|
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
|
||||||
|
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
|
||||||
|
MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
|
||||||
|
MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
|
||||||
|
MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
|
||||||
|
|
||||||
|
CEQI 011110 000 .. ..... ..... ..... 000111 @s5
|
||||||
|
CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
|
||||||
|
CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
|
||||||
|
CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
|
||||||
|
CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
|
||||||
|
|
||||||
|
LDI 011110 110 .. .......... ..... 000111 @ldi
|
||||||
|
|
||||||
|
SLLI 011110 000 ....... ..... ..... 001001 @bit
|
||||||
|
SRAI 011110 001 ....... ..... ..... 001001 @bit
|
||||||
|
SRLI 011110 010 ....... ..... ..... 001001 @bit
|
||||||
|
BCLRI 011110 011 ....... ..... ..... 001001 @bit
|
||||||
|
BSETI 011110 100 ....... ..... ..... 001001 @bit
|
||||||
|
BNEGI 011110 101 ....... ..... ..... 001001 @bit
|
||||||
|
BINSLI 011110 110 ....... ..... ..... 001001 @bit
|
||||||
|
BINSRI 011110 111 ....... ..... ..... 001001 @bit
|
||||||
|
|
||||||
|
SAT_S 011110 000 ....... ..... ..... 001010 @bit
|
||||||
|
SAT_U 011110 001 ....... ..... ..... 001010 @bit
|
||||||
|
SRARI 011110 010 ....... ..... ..... 001010 @bit
|
||||||
|
SRLRI 011110 011 ....... ..... ..... 001010 @bit
|
||||||
|
|
||||||
|
SLL 011110 000.. ..... ..... ..... 001101 @3r
|
||||||
|
SRA 011110 001.. ..... ..... ..... 001101 @3r
|
||||||
|
SRL 011110 010.. ..... ..... ..... 001101 @3r
|
||||||
|
BCLR 011110 011.. ..... ..... ..... 001101 @3r
|
||||||
|
BSET 011110 100.. ..... ..... ..... 001101 @3r
|
||||||
|
BNEG 011110 101.. ..... ..... ..... 001101 @3r
|
||||||
|
BINSL 011110 110.. ..... ..... ..... 001101 @3r
|
||||||
|
BINSR 011110 111.. ..... ..... ..... 001101 @3r
|
||||||
|
|
||||||
|
ADDV 011110 000.. ..... ..... ..... 001110 @3r
|
||||||
|
SUBV 011110 001.. ..... ..... ..... 001110 @3r
|
||||||
|
MAX_S 011110 010.. ..... ..... ..... 001110 @3r
|
||||||
|
MAX_U 011110 011.. ..... ..... ..... 001110 @3r
|
||||||
|
MIN_S 011110 100.. ..... ..... ..... 001110 @3r
|
||||||
|
MIN_U 011110 101.. ..... ..... ..... 001110 @3r
|
||||||
|
MAX_A 011110 110.. ..... ..... ..... 001110 @3r
|
||||||
|
MIN_A 011110 111.. ..... ..... ..... 001110 @3r
|
||||||
|
|
||||||
|
CEQ 011110 000.. ..... ..... ..... 001111 @3r
|
||||||
|
CLT_S 011110 010.. ..... ..... ..... 001111 @3r
|
||||||
|
CLT_U 011110 011.. ..... ..... ..... 001111 @3r
|
||||||
|
CLE_S 011110 100.. ..... ..... ..... 001111 @3r
|
||||||
|
CLE_U 011110 101.. ..... ..... ..... 001111 @3r
|
||||||
|
|
||||||
|
ADD_A 011110 000.. ..... ..... ..... 010000 @3r
|
||||||
|
ADDS_A 011110 001.. ..... ..... ..... 010000 @3r
|
||||||
|
ADDS_S 011110 010.. ..... ..... ..... 010000 @3r
|
||||||
|
ADDS_U 011110 011.. ..... ..... ..... 010000 @3r
|
||||||
|
AVE_S 011110 100.. ..... ..... ..... 010000 @3r
|
||||||
|
AVE_U 011110 101.. ..... ..... ..... 010000 @3r
|
||||||
|
AVER_S 011110 110.. ..... ..... ..... 010000 @3r
|
||||||
|
AVER_U 011110 111.. ..... ..... ..... 010000 @3r
|
||||||
|
|
||||||
|
SUBS_S 011110 000.. ..... ..... ..... 010001 @3r
|
||||||
|
SUBS_U 011110 001.. ..... ..... ..... 010001 @3r
|
||||||
|
SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r
|
||||||
|
SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r
|
||||||
|
ASUB_S 011110 100.. ..... ..... ..... 010001 @3r
|
||||||
|
ASUB_U 011110 101.. ..... ..... ..... 010001 @3r
|
||||||
|
|
||||||
|
MULV 011110 000.. ..... ..... ..... 010010 @3r
|
||||||
|
MADDV 011110 001.. ..... ..... ..... 010010 @3r
|
||||||
|
MSUBV 011110 010.. ..... ..... ..... 010010 @3r
|
||||||
|
DIV_S 011110 100.. ..... ..... ..... 010010 @3r
|
||||||
|
DIV_U 011110 101.. ..... ..... ..... 010010 @3r
|
||||||
|
MOD_S 011110 110.. ..... ..... ..... 010010 @3r
|
||||||
|
MOD_U 011110 111.. ..... ..... ..... 010010 @3r
|
||||||
|
|
||||||
|
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
|
||||||
|
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
|
||||||
|
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
|
||||||
|
DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
|
||||||
|
DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
|
||||||
|
DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
|
||||||
|
|
||||||
|
SLD 011110 000 .. ..... ..... ..... 010100 @3r
|
||||||
|
SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
|
||||||
|
PCKEV 011110 010 .. ..... ..... ..... 010100 @3r
|
||||||
|
PCKOD 011110 011 .. ..... ..... ..... 010100 @3r
|
||||||
|
ILVL 011110 100 .. ..... ..... ..... 010100 @3r
|
||||||
|
ILVR 011110 101 .. ..... ..... ..... 010100 @3r
|
||||||
|
ILVEV 011110 110 .. ..... ..... ..... 010100 @3r
|
||||||
|
ILVOD 011110 111 .. ..... ..... ..... 010100 @3r
|
||||||
|
|
||||||
|
VSHF 011110 000 .. ..... ..... ..... 010101 @3r
|
||||||
|
SRAR 011110 001 .. ..... ..... ..... 010101 @3r
|
||||||
|
SRLR 011110 010 .. ..... ..... ..... 010101 @3r
|
||||||
|
HADD_S 011110 100.. ..... ..... ..... 010101 @3r
|
||||||
|
HADD_U 011110 101.. ..... ..... ..... 010101 @3r
|
||||||
|
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
|
||||||
|
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
|
||||||
|
|
||||||
|
{
|
||||||
|
CTCMSA 011110 0000111110 ..... ..... 011001 @elm
|
||||||
|
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
|
||||||
|
}
|
||||||
|
{
|
||||||
|
CFCMSA 011110 0001111110 ..... ..... 011001 @elm
|
||||||
|
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
|
||||||
|
}
|
||||||
|
{
|
||||||
|
MOVE_V 011110 0010111110 ..... ..... 011001 @elm
|
||||||
|
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
|
||||||
|
}
|
||||||
|
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
|
||||||
|
INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
|
||||||
|
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
|
||||||
|
|
||||||
|
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w
|
||||||
|
|
||||||
|
FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w
|
||||||
|
|
||||||
|
FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w
|
||||||
|
MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h
|
||||||
|
|
||||||
|
AND_V 011110 00000 ..... ..... ..... 011110 @vec
|
||||||
|
OR_V 011110 00001 ..... ..... ..... 011110 @vec
|
||||||
|
NOR_V 011110 00010 ..... ..... ..... 011110 @vec
|
||||||
|
XOR_V 011110 00011 ..... ..... ..... 011110 @vec
|
||||||
|
BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
|
||||||
|
BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
|
||||||
|
BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
|
||||||
|
FILL 011110 11000000 .. ..... ..... 011110 @2r
|
||||||
|
PCNT 011110 11000001 .. ..... ..... 011110 @2r
|
||||||
|
NLOC 011110 11000010 .. ..... ..... 011110 @2r
|
||||||
|
NLZC 011110 11000011 .. ..... ..... 011110 @2r
|
||||||
|
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
|
||||||
|
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
|
||||||
|
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
|
||||||
|
FSQRT 011110 110010011 . ..... ..... 011110 @2rf
|
||||||
|
FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
|
||||||
|
FRCP 011110 110010101 . ..... ..... 011110 @2rf
|
||||||
|
FRINT 011110 110010110 . ..... ..... 011110 @2rf
|
||||||
|
FLOG2 011110 110010111 . ..... ..... 011110 @2rf
|
||||||
|
FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
|
||||||
|
FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
|
||||||
|
FFQL 011110 110011010 . ..... ..... 011110 @2rf
|
||||||
|
FFQR 011110 110011011 . ..... ..... 011110 @2rf
|
||||||
|
FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
|
||||||
|
FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
|
||||||
|
FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
|
||||||
|
FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
|
||||||
|
|
||||||
|
LD 011110 .......... ..... ..... 1000 .. @ldst
|
||||||
|
ST 011110 .......... ..... ..... 1001 .. @ldst
|
||||||
|
@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
|
|||||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||||
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
|
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
|
||||||
|
|
||||||
pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
|
pwd->b[0] = msa_maddv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
|
||||||
pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
|
pwd->b[1] = msa_maddv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
|
||||||
pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
|
pwd->b[2] = msa_maddv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
|
||||||
pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
|
pwd->b[3] = msa_maddv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
|
||||||
pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
|
pwd->b[4] = msa_maddv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
|
||||||
pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
|
pwd->b[5] = msa_maddv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
|
||||||
pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
|
pwd->b[6] = msa_maddv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
|
||||||
pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
|
pwd->b[7] = msa_maddv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
|
||||||
pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
|
pwd->b[8] = msa_maddv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
|
||||||
pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
|
pwd->b[9] = msa_maddv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
|
||||||
pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
|
pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
|
||||||
pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
|
pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
|
||||||
pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
|
pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
|
||||||
pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
|
pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
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||||||
pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
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pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
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||||||
pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
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pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
|
||||||
}
|
}
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||||||
|
|
||||||
void helper_msa_maddv_h(CPUMIPSState *env,
|
void helper_msa_maddv_h(CPUMIPSState *env,
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||||||
@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env,
|
|||||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||||
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
|
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
|
||||||
|
|
||||||
pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
|
pwd->b[0] = msa_msubv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
|
||||||
pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
|
pwd->b[1] = msa_msubv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
|
||||||
pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
|
pwd->b[2] = msa_msubv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
|
||||||
pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
|
pwd->b[3] = msa_msubv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
|
||||||
pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
|
pwd->b[4] = msa_msubv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
|
||||||
pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
|
pwd->b[5] = msa_msubv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
|
||||||
pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
|
pwd->b[6] = msa_msubv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
|
||||||
pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
|
pwd->b[7] = msa_msubv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
|
||||||
pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
|
pwd->b[8] = msa_msubv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
|
||||||
pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
|
pwd->b[9] = msa_msubv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
|
||||||
pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
|
pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
|
||||||
pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
|
pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
|
||||||
pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
|
pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
|
||||||
pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
|
pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
|
||||||
pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
|
pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
|
||||||
pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
|
pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
|
||||||
}
|
}
|
||||||
|
|
||||||
void helper_msa_msubv_h(CPUMIPSState *env,
|
void helper_msa_msubv_h(CPUMIPSState *env,
|
||||||
|
File diff suppressed because it is too large
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Reference in New Issue
Block a user