target-arm: Add MDCR_EL2
Add the MDCR_EL2 register. We don't implement any of the debug-related traps this register controls yet, so currently it simply reads back as written. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message; moved non-dummy definition from debug_cp_reginfo to el2_cp_reginfo.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -380,6 +380,7 @@ typedef struct CPUARMState {
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uint64_t dbgwcr[16]; /* watchpoint control registers */
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uint64_t mdscr_el1;
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uint64_t oslsr_el1; /* OS Lock Status */
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uint64_t mdcr_el2;
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/* If the counter is enabled, this stores the last time the counter
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* was reset. Otherwise it stores the counter value
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*/
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@ -3227,6 +3227,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
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{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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@ -3448,6 +3451,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
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.resetvalue = 0,
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.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
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#endif
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/* The only field of MDCR_EL2 that has a defined architectural reset value
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* is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
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* don't impelment any PMU event counters, so using zero as a reset
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* value for MDCR_EL2 is okay
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*/
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{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
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REGINFO_SENTINEL
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};
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