hw/display: misc fixes
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJbe8pBAAoJEEy22O7T6HE4RtYQANUISQwb3Dlijw9PApNH735W IiZeHltSvKUxPd7C+Pp2yQkmwih3cjwBZO8jpihix65fZ4shsmLjWR9MFkEG2876 YqlxtddDV+y+6S7YQHlb59mBJD14+SmRiFbzfa7NWxnM2x6Lp2otcs1J06ajuauv +SwUkLHikEZZKN4UsW/bvdJHSuOrx7sQKpWMFbnHM/Ki4WknQfgrvGWpnizhFH4z 8hgE+rhgXZBvLEfYV4CAFtJFb8rPEsh6NgsRfYHBmQDSexS2hpR1bHugpgNSvot0 +5c55q7S3Zfv8GIvFC0nlFZhBKFsFWaYVO/UlBpCRWNkp3Xu5whKxx6vhKJ0VEVn 3IXW4a1s/nY1b/2W/u7v6OdVZHIEggtjseelKUTQzM5GQGhqwhujJ72o13ySg9bm a89WoBPAQvkRDoynqWwPatgE7K2JLq6pEI+jtInNd0w7L+H2iUcfnol9Z5t1d21w 7uiLvUpm9htvmXlOJVI9lAicGaUMAVp4eDk3X+RRopAasdNQdHhzVyiRRsBZC5UR cVJKyCJ0mi8pIOQJ5MjNvYG2+djHCK/rOsGgLOOcrm3DwzNo9TkQFBX0FBgbSPvI LCszJdfnKaxVsq9PvCIqWaLkDQiKrKk57nP7KF4YwRRNCCzJg70p3h8K0phpReHN 0yXJUYzxsPrm9MI48LY4 =Z0sM -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180821-pull-request' into staging hw/display: misc fixes # gpg: Signature made Tue 21 Aug 2018 09:16:01 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20180821-pull-request: hw/pci-host/bonito: Move away from old_mmio accessors hw/display/vga-isa-mm: Convert away from old_mmio qxl: drop unused generation variable hw/display/ramfb: Compile the ramfb code only when CONFIG_FW_CFG_DMA is set Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
13b7b18850
@ -1,5 +1,5 @@
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common-obj-y += ramfb.o
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common-obj-$(CONFIG_FW_CFG_DMA) += ramfb.o
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common-obj-y += ramfb-standalone.o
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common-obj-$(CONFIG_FW_CFG_DMA) += ramfb-standalone.o
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common-obj-$(CONFIG_ADS7846) += ads7846.o
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common-obj-$(CONFIG_ADS7846) += ads7846.o
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common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
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common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
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@ -2057,7 +2057,6 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
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qemu_spice_display_init_common(&qxl->ssd);
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qemu_spice_display_init_common(&qxl->ssd);
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qxl->mode = QXL_MODE_UNDEFINED;
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qxl->mode = QXL_MODE_UNDEFINED;
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qxl->generation = 1;
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qxl->num_memslots = NUM_MEMSLOTS;
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qxl->num_memslots = NUM_MEMSLOTS;
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qemu_mutex_init(&qxl->track_lock);
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qemu_mutex_init(&qxl->track_lock);
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qemu_mutex_init(&qxl->async_lock);
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qemu_mutex_init(&qxl->async_lock);
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@ -43,7 +43,6 @@ typedef struct PCIQXLDevice {
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enum qxl_mode mode;
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enum qxl_mode mode;
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uint32_t cmdflags;
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uint32_t cmdflags;
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int generation;
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uint32_t revision;
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uint32_t revision;
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int32_t num_memslots;
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int32_t num_memslots;
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@ -36,64 +36,30 @@ typedef struct ISAVGAMMState {
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} ISAVGAMMState;
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} ISAVGAMMState;
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/* Memory mapped interface */
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/* Memory mapped interface */
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static uint32_t vga_mm_readb (void *opaque, hwaddr addr)
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static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size)
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{
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{
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ISAVGAMMState *s = opaque;
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ISAVGAMMState *s = opaque;
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return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
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return vga_ioport_read(&s->vga, addr >> s->it_shift) &
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MAKE_64BIT_MASK(0, size * 8);
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}
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}
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static void vga_mm_writeb (void *opaque,
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static void vga_mm_write(void *opaque, hwaddr addr, uint64_t value,
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hwaddr addr, uint32_t value)
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unsigned size)
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{
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{
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ISAVGAMMState *s = opaque;
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ISAVGAMMState *s = opaque;
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vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
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vga_ioport_write(&s->vga, addr >> s->it_shift,
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}
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value & MAKE_64BIT_MASK(0, size * 8));
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static uint32_t vga_mm_readw (void *opaque, hwaddr addr)
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{
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ISAVGAMMState *s = opaque;
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return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
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}
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static void vga_mm_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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ISAVGAMMState *s = opaque;
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vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
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}
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static uint32_t vga_mm_readl (void *opaque, hwaddr addr)
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{
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ISAVGAMMState *s = opaque;
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return vga_ioport_read(&s->vga, addr >> s->it_shift);
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}
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static void vga_mm_writel (void *opaque,
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hwaddr addr, uint32_t value)
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{
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ISAVGAMMState *s = opaque;
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vga_ioport_write(&s->vga, addr >> s->it_shift, value);
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}
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}
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static const MemoryRegionOps vga_mm_ctrl_ops = {
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static const MemoryRegionOps vga_mm_ctrl_ops = {
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.old_mmio = {
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.read = vga_mm_read,
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.read = {
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.write = vga_mm_write,
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vga_mm_readb,
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.valid.min_access_size = 1,
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vga_mm_readw,
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.valid.max_access_size = 4,
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vga_mm_readl,
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.impl.min_access_size = 1,
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},
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.impl.max_access_size = 4,
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.write = {
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vga_mm_writeb,
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vga_mm_writew,
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vga_mm_writel,
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},
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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@ -460,8 +460,8 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
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return pciaddr;
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return pciaddr;
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}
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}
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static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
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static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
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uint32_t val)
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unsigned size)
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{
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{
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PCIBonitoState *s = opaque;
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIDevice *d = PCI_DEVICE(s);
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@ -469,34 +469,8 @@ static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
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uint32_t pciaddr;
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uint32_t pciaddr;
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uint16_t status;
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uint16_t status;
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DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
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DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n",
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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addr, size, val);
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if (pciaddr == 0xffffffff) {
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return;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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}
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static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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uint32_t val)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
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assert((addr & 0x1) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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@ -506,7 +480,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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/* set the pci address in s->config_reg */
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val, 2);
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pci_data_write(phb->bus, phb->config_reg, val, size);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status = pci_get_word(d->config + PCI_STATUS);
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@ -514,8 +488,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
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pci_set_word(d->config + PCI_STATUS, status);
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pci_set_word(d->config + PCI_STATUS, status);
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}
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}
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static void bonito_spciconf_writel(void *opaque, hwaddr addr,
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static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
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uint32_t val)
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{
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{
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PCIBonitoState *s = opaque;
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIDevice *d = PCI_DEVICE(s);
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@ -523,38 +496,12 @@ static void bonito_spciconf_writel(void *opaque, hwaddr addr,
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uint32_t pciaddr;
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uint32_t pciaddr;
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uint16_t status;
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uint16_t status;
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DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
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DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
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assert((addr & 0x3) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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if (pciaddr == 0xffffffff) {
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return;
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return MAKE_64BIT_MASK(0, size * 8);
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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pci_data_write(phb->bus, phb->config_reg, val, 4);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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}
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static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xff;
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}
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}
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/* set the pci address in s->config_reg */
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/* set the pci address in s->config_reg */
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@ -565,79 +512,17 @@ static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 1);
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return pci_data_read(phb->bus, phb->config_reg, size);
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}
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static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
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assert((addr & 0x1) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xffff;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 2);
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}
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static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
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{
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PCIBonitoState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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uint32_t pciaddr;
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uint16_t status;
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DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
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assert((addr & 0x3) == 0);
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pciaddr = bonito_sbridge_pciaddr(s, addr);
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if (pciaddr == 0xffffffff) {
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return 0xffffffff;
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}
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/* set the pci address in s->config_reg */
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phb->config_reg = (pciaddr) | (1u << 31);
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/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
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status = pci_get_word(d->config + PCI_STATUS);
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status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
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pci_set_word(d->config + PCI_STATUS, status);
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return pci_data_read(phb->bus, phb->config_reg, 4);
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}
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}
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/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
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/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
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static const MemoryRegionOps bonito_spciconf_ops = {
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static const MemoryRegionOps bonito_spciconf_ops = {
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.old_mmio = {
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.read = bonito_spciconf_read,
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.read = {
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.write = bonito_spciconf_write,
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bonito_spciconf_readb,
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.valid.min_access_size = 1,
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bonito_spciconf_readw,
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.valid.max_access_size = 4,
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bonito_spciconf_readl,
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.impl.min_access_size = 1,
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},
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.impl.max_access_size = 4,
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.write = {
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bonito_spciconf_writeb,
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bonito_spciconf_writew,
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bonito_spciconf_writel,
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},
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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