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hw/display: misc fixes

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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180821-pull-request' into staging

hw/display: misc fixes

# gpg: Signature made Tue 21 Aug 2018 09:16:01 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/vga-20180821-pull-request:
  hw/pci-host/bonito: Move away from old_mmio accessors
  hw/display/vga-isa-mm: Convert away from old_mmio
  qxl: drop unused generation variable
  hw/display/ramfb: Compile the ramfb code only when CONFIG_FW_CFG_DMA is set

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-08-21 15:57:56 +01:00
commit 13b7b18850
5 changed files with 30 additions and 181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/display/Makefile.objs
View File

@ -1,5 +1,5 @@
common-obj-y += ramfb.o
common-obj-y += ramfb-standalone.o
common-obj-$(CONFIG_FW_CFG_DMA) += ramfb.o
common-obj-$(CONFIG_FW_CFG_DMA) += ramfb-standalone.o
common-obj-$(CONFIG_ADS7846) += ads7846.o
common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o

1
hw/display/qxl.c
View File

@ -2057,7 +2057,6 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
qemu_spice_display_init_common(&qxl->ssd);
qxl->mode = QXL_MODE_UNDEFINED;
qxl->generation = 1;
qxl->num_memslots = NUM_MEMSLOTS;
qemu_mutex_init(&qxl->track_lock);
qemu_mutex_init(&qxl->async_lock);

1
hw/display/qxl.h
View File

@ -43,7 +43,6 @@ typedef struct PCIQXLDevice {
enum qxl_mode mode;
uint32_t cmdflags;
int generation;
uint32_t revision;
int32_t num_memslots;

60
hw/display/vga-isa-mm.c
View File

@ -36,64 +36,30 @@ typedef struct ISAVGAMMState {
} ISAVGAMMState;
/* Memory mapped interface */
static uint32_t vga_mm_readb (void *opaque, hwaddr addr)
static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size)
{
ISAVGAMMState *s = opaque;
return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
return vga_ioport_read(&s->vga, addr >> s->it_shift) &
MAKE_64BIT_MASK(0, size * 8);
}
static void vga_mm_writeb (void *opaque,
hwaddr addr, uint32_t value)
static void vga_mm_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
}
static uint32_t vga_mm_readw (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
}
static void vga_mm_writew (void *opaque,
hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
}
static uint32_t vga_mm_readl (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
return vga_ioport_read(&s->vga, addr >> s->it_shift);
}
static void vga_mm_writel (void *opaque,
hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value);
vga_ioport_write(&s->vga, addr >> s->it_shift,
value & MAKE_64BIT_MASK(0, size * 8));
}
static const MemoryRegionOps vga_mm_ctrl_ops = {
.old_mmio = {
.read = {
vga_mm_readb,
vga_mm_readw,
vga_mm_readl,
},
.write = {
vga_mm_writeb,
vga_mm_writew,
vga_mm_writel,
},
},
.read = vga_mm_read,
.write = vga_mm_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};

145
hw/pci-host/bonito.c
View File

@ -460,8 +460,8 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
return pciaddr;
}
static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
uint32_t val)
static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@ -469,34 +469,8 @@ static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
return;
}
/* set the pci address in s->config_reg */
phb->config_reg = (pciaddr) | (1u << 31);
pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1);
/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
status = pci_get_word(d->config + PCI_STATUS);
status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
pci_set_word(d->config + PCI_STATUS, status);
}
static void bonito_spciconf_writew(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr & 0x1) == 0);
DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n",
addr, size, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@ -506,7 +480,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
/* set the pci address in s->config_reg */
phb->config_reg = (pciaddr) | (1u << 31);
pci_data_write(phb->bus, phb->config_reg, val, 2);
pci_data_write(phb->bus, phb->config_reg, val, size);
/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
status = pci_get_word(d->config + PCI_STATUS);
@ -514,8 +488,7 @@ static void bonito_spciconf_writew(void *opaque, hwaddr addr,
pci_set_word(d->config + PCI_STATUS, status);
}
static void bonito_spciconf_writel(void *opaque, hwaddr addr,
uint32_t val)
static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@ -523,38 +496,12 @@ static void bonito_spciconf_writel(void *opaque, hwaddr addr,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr & 0x3) == 0);
DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
return;
}
/* set the pci address in s->config_reg */
phb->config_reg = (pciaddr) | (1u << 31);
pci_data_write(phb->bus, phb->config_reg, val, 4);
/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
status = pci_get_word(d->config + PCI_STATUS);
status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
pci_set_word(d->config + PCI_STATUS, status);
}
static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
return 0xff;
return MAKE_64BIT_MASK(0, size * 8);
}
/* set the pci address in s->config_reg */
@ -565,79 +512,17 @@ static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
pci_set_word(d->config + PCI_STATUS, status);
return pci_data_read(phb->bus, phb->config_reg, 1);
}
static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
assert((addr & 0x1) == 0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
return 0xffff;
}
/* set the pci address in s->config_reg */
phb->config_reg = (pciaddr) | (1u << 31);
/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
status = pci_get_word(d->config + PCI_STATUS);
status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
pci_set_word(d->config + PCI_STATUS, status);
return pci_data_read(phb->bus, phb->config_reg, 2);
}
static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
assert((addr & 0x3) == 0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
return 0xffffffff;
}
/* set the pci address in s->config_reg */
phb->config_reg = (pciaddr) | (1u << 31);
/* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
status = pci_get_word(d->config + PCI_STATUS);
status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
pci_set_word(d->config + PCI_STATUS, status);
return pci_data_read(phb->bus, phb->config_reg, 4);
return pci_data_read(phb->bus, phb->config_reg, size);
}
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
static const MemoryRegionOps bonito_spciconf_ops = {
.old_mmio = {
.read = {
bonito_spciconf_readb,
bonito_spciconf_readw,
bonito_spciconf_readl,
},
.write = {
bonito_spciconf_writeb,
bonito_spciconf_writew,
bonito_spciconf_writel,
},
},
.read = bonito_spciconf_read,
.write = bonito_spciconf_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.impl.min_access_size = 1,
.impl.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};