mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions

Browse Source 
To keep consistency with the machine* functions, remove the riscv_
prefix of the soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1590072147-13035-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1590072147-13035-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-05-21 07:42:26 -07:00 committed by Alistair Francis
parent 087a424674
commit 139177b1d4
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
hw/riscv/sifive_u.c
View File

@ -481,7 +481,7 @@ static void sifive_u_machine_init_register_types(void)
type_init(sifive_u_machine_init_register_types) type_init(sifive_u_machine_init_register_types)
static void riscv_sifive_u_soc_init(Object *obj) static void sifive_u_soc_instance_init(Object *obj)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj); SiFiveUSoCState *s = RISCV_U_SOC(obj);
@ -520,7 +520,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM); TYPE_CADENCE_GEM);
} }
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(dev); SiFiveUSoCState *s = RISCV_U_SOC(dev);
@ -635,32 +635,32 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
} }
static Property riscv_sifive_u_soc_props[] = { static Property sifive_u_soc_props[] = {
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, riscv_sifive_u_soc_props); device_class_set_props(dc, sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize; dc->realize = sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false; dc->user_creatable = false;
} }
static const TypeInfo riscv_sifive_u_soc_type_info = { static const TypeInfo sifive_u_soc_type_info = {
.name = TYPE_RISCV_U_SOC, .name = TYPE_RISCV_U_SOC,
.parent = TYPE_DEVICE, .parent = TYPE_DEVICE,
.instance_size = sizeof(SiFiveUSoCState), .instance_size = sizeof(SiFiveUSoCState),
.instance_init = riscv_sifive_u_soc_init, .instance_init = sifive_u_soc_instance_init,
.class_init = riscv_sifive_u_soc_class_init, .class_init = sifive_u_soc_class_init,
}; };
static void riscv_sifive_u_soc_register_types(void) static void sifive_u_soc_register_types(void)
{ {
type_register_static(&riscv_sifive_u_soc_type_info); type_register_static(&sifive_u_soc_type_info);
} }
type_init(riscv_sifive_u_soc_register_types) type_init(sifive_u_soc_register_types)