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target/i386: Fix BLSR and BLSI

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The implementation of these two instructions was swapped.
At the same time, unify the setup of eflags for the insn group.

Reported-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170712192902.15493-1-rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Richard Henderson 2017-07-12 09:29:02 -10:00 committed by Paolo Bonzini
parent 019288bf13
commit 13672386a9
1 changed files with 12 additions and 20 deletions
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32
target/i386/translate.c
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@ -4059,34 +4059,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
switch (reg & 7) {
case 1: /* blsr By,Ey */
tcg_gen_subi_tl(cpu_T1, cpu_T0, 1);
tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
break;
case 2: /* blsmsk By,Ey */
tcg_gen_subi_tl(cpu_T1, cpu_T0, 1);
tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_T1);
break;
case 3: /* blsi By, Ey */
tcg_gen_neg_tl(cpu_T1, cpu_T0);
tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_mov_reg_v(ot, s->vex_v, cpu_T0);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 2: /* blsmsk By,Ey */
tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 3: /* blsi By, Ey */
tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
default:
goto unknown_op;
}
tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
gen_op_mov_reg_v(ot, s->vex_v, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
default: