target/arm: Mark up sysregs for HFGITR bits 12..17
Mark up the sysreg definitions for the system instructions trapped by HFGITR bits 12..17. These bits cover AT address translation instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
This commit is contained in:
parent
dd34565319
commit
132c98cd93
@ -660,6 +660,12 @@ typedef enum FGTBit {
|
||||
DO_BIT(HFGITR, DCCVADP),
|
||||
DO_BIT(HFGITR, DCCIVAC),
|
||||
DO_BIT(HFGITR, DCZVA),
|
||||
DO_BIT(HFGITR, ATS1E1R),
|
||||
DO_BIT(HFGITR, ATS1E1W),
|
||||
DO_BIT(HFGITR, ATS1E0R),
|
||||
DO_BIT(HFGITR, ATS1E0W),
|
||||
DO_BIT(HFGITR, ATS1E1RP),
|
||||
DO_BIT(HFGITR, ATS1E1WP),
|
||||
} FGTBit;
|
||||
|
||||
#undef DO_BIT
|
||||
|
@ -5400,18 +5400,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
|
||||
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E1R,
|
||||
.writefn = ats_write64 },
|
||||
{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E1W,
|
||||
.writefn = ats_write64 },
|
||||
{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E0R,
|
||||
.writefn = ats_write64 },
|
||||
{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E0W,
|
||||
.writefn = ats_write64 },
|
||||
{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
|
||||
@ -7880,10 +7884,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
|
||||
{ .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E1RP,
|
||||
.writefn = ats_write64 },
|
||||
{ .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
|
||||
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
|
||||
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
|
||||
.fgt = FGT_ATS1E1WP,
|
||||
.writefn = ats_write64 },
|
||||
};
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user