hw/net/can/xlnx-versal-canfd: Simplify DLC conversions
Use QEMU's helper functions can_dlc2len() and can_len2dlc() for translating between the raw DLC value and the SocketCAN length value. This also has the side effect of correctly handling received CAN FD frames with a DLC of 0-8, which was broken previously. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240827034927.66659-7-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -678,8 +678,6 @@ REG32(RB_DW15_REGISTER_1, 0x4144)
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FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8)
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FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8)
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static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32, 48, 64};
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static void canfd_update_irq(XlnxVersalCANFDState *s)
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{
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const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] &
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@ -897,59 +895,19 @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
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}
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if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) {
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/*
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* CANFD frame.
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* Converting dlc(0 to 15) 4 Byte data to plain length(i.e. 0 to 64)
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* 1 Byte data. This is done to make it work with SocketCAN.
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* On actual CANFD frame, this value can't be more than 0xF.
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* Conversion table for DLC to plain length:
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*
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* DLC Plain Length
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* 0 - 8 0 - 8
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* 9 9 - 12
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* 10 13 - 16
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* 11 17 - 20
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* 12 21 - 24
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* 13 25 - 32
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* 14 33 - 48
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* 15 49 - 64
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*/
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frame->flags |= QEMU_CAN_FRMF_TYPE_FD;
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if (dlc_value < 8) {
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frame->can_dlc = dlc_value;
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} else {
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assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array));
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frame->can_dlc = canfd_dlc_array[dlc_value - 8];
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}
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if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) {
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frame->flags |= QEMU_CAN_FRMF_BRS;
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}
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} else {
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/*
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* FD Format bit not set that means it is a CAN Frame.
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* Conversion table for classic CAN:
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*
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* DLC Plain Length
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* 0 - 7 0 - 7
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* 8 - 15 8
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*/
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if (dlc_value > 8) {
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frame->can_dlc = 8;
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qemu_log_mask(LOG_GUEST_ERROR, "Maximum DLC value for Classic CAN"
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" frame is 8. Only 8 byte data will be sent.\n");
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} else {
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frame->can_dlc = dlc_value;
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}
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if (is_rtr) {
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frame->can_id |= QEMU_CAN_RTR_FLAG;
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}
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}
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frame->can_dlc = can_dlc2len(dlc_value);
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for (j = 0; j < frame->can_dlc; j++) {
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val = 8 * (3 - i);
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@ -1007,7 +965,6 @@ static void store_rx_sequential(XlnxVersalCANFDState *s,
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bool rx_fifo_id, uint8_t filter_index)
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{
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int i;
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bool is_canfd_frame;
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uint8_t dlc = frame->can_dlc;
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uint8_t rx_reg_num = 0;
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uint32_t dlc_reg_val = 0;
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@ -1053,17 +1010,10 @@ static void store_rx_sequential(XlnxVersalCANFDState *s,
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s->regs[store_location] = frame_to_reg_id(frame);
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dlc = frame->can_dlc;
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dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc));
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if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) {
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is_canfd_frame = true;
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/* Store dlc value in Xilinx specific format. */
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for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) {
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if (canfd_dlc_array[i] == frame->can_dlc) {
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dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i);
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}
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}
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1);
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if (frame->flags & QEMU_CAN_FRMF_BRS) {
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1);
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@ -1071,17 +1021,8 @@ static void store_rx_sequential(XlnxVersalCANFDState *s,
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if (frame->flags & QEMU_CAN_FRMF_ESI) {
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1);
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}
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} else {
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is_canfd_frame = false;
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if (frame->can_dlc > 8) {
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dlc = 8;
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}
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dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, dlc);
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}
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, is_canfd_frame);
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp);
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dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX,
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filter_index);
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