ARM: exynos4210: MCT support.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -346,7 +346,7 @@ obj-arm-y += versatile_pci.o
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obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
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obj-arm-y += exynos4210_pmu.o
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obj-arm-y += exynos4210_pmu.o exynos4210_mct.o
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obj-arm-y += arm_l2x0.o
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obj-arm-y += arm_mptimer.o
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obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
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@ -32,6 +32,9 @@
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/* PWM */
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#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
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/* MCT */
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#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
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/* UART's definitions */
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#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
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#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
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@ -220,6 +223,22 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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s->irq_table[exynos4210_get_irq(22, 4)],
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NULL);
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/* Multi Core Timer */
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dev = qdev_create(NULL, "exynos4210.mct");
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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for (n = 0; n < 4; n++) {
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/* Connect global timer interrupts to Combiner gpio_in */
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sysbus_connect_irq(busdev, n,
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s->irq_table[exynos4210_get_irq(1, 4 + n)]);
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}
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/* Connect local timer interrupts to Combiner gpio_in */
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sysbus_connect_irq(busdev, 4,
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s->irq_table[exynos4210_get_irq(51, 0)]);
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sysbus_connect_irq(busdev, 5,
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s->irq_table[exynos4210_get_irq(35, 3)]);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
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/*** UARTs ***/
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exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
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EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
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1488
hw/exynos4210_mct.c
Normal file
1488
hw/exynos4210_mct.c
Normal file
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