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x86_iommu/amd: Enable Guest virtual APIC support

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Now that amd-iommu support interrupt remapping, enable the GASup in IVRS
table and GASup in extended feature register to indicate that IOMMU
support guest virtual APIC mode. GASup provides option to guest OS to
make use of 128-bit IRTE.

Note that the GAMSup is set to zero to indicate that amd-iommu does not
support guest virtual APIC mode (aka AVIC) which would be used for the
nested VMs.

See Table 21 from IOMMU spec for interrupt virtualization controls

Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Singh, Brijesh 2018-10-01 19:44:45 +00:00 committed by Michael S. Tsirkin
parent 135f866e60
commit 12499b2331
2 changed files with 8 additions and 7 deletions
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3
hw/i386/acpi-build.c
View File

@ -2518,7 +2518,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker)
build_append_int_noprefix(table_data,
(48UL << 30) | /* HATS */
(48UL << 28) | /* GATS */
(1UL << 2), /* GTSup */
(1UL << 2) | /* GTSup */
(1UL << 6), /* GASup */
4);
/*
* Type 1 device entry reporting all devices

12
hw/i386/amd_iommu.h
View File

@ -176,7 +176,7 @@
/* extended feature support */
#define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \
AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \
AMDVI_GATS_MODE | AMDVI_HATS_MODE)
AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA)
/* capabilities header */
#define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \
@ -242,11 +242,11 @@
#define AMDVI_IOAPIC_INT_TYPE_EINT 0x7
/* Pass through interrupt */
#define AMDVI_DEV_INT_PASS_MASK (1UL << 56)
#define AMDVI_DEV_EINT_PASS_MASK (1UL << 57)
#define AMDVI_DEV_NMI_PASS_MASK (1UL << 58)
#define AMDVI_DEV_LINT0_PASS_MASK (1UL << 62)
#define AMDVI_DEV_LINT1_PASS_MASK (1UL << 63)
#define AMDVI_DEV_INT_PASS_MASK (1ULL << 56)
#define AMDVI_DEV_EINT_PASS_MASK (1ULL << 57)
#define AMDVI_DEV_NMI_PASS_MASK (1ULL << 58)
#define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62)
#define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63)
/* Interrupt remapping table fields (Guest VAPIC not enabled) */
union irte {