target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoder
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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6476902740
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11ffaf8c73
@ -450,6 +450,50 @@ static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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*entry = *decode_by_prefix(s, opcodes_0F7F);
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}
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static void decode_0FB8(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry popcnt =
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X86_OP_ENTRYwr(POPCNT, G,v, E,v, cpuid(POPCNT) zextT0);
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if (s->prefix & PREFIX_REPZ) {
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*entry = popcnt;
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} else {
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memset(entry, 0, sizeof(*entry));
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}
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}
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static void decode_0FBC(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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/* For BSF, pass 2op as the third operand so that we can use zextT0 */
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static const X86OpEntry opcodes_0FBC[4] = {
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X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0),
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X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0), /* 0x66 */
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X86_OP_ENTRYwr(TZCNT, G,v, E,v, zextT0), /* 0xf3 */
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X86_OP_ENTRY3(BSF, G,v, E,v, 2op,v, zextT0), /* 0xf2 */
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};
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if (!(s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
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*entry = opcodes_0FBC[0];
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} else {
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*entry = *decode_by_prefix(s, opcodes_0FBC);
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}
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}
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static void decode_0FBD(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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/* For BSR, pass 2op as the third operand so that we can use zextT0 */
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static const X86OpEntry opcodes_0FBD[4] = {
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X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0),
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X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0), /* 0x66 */
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X86_OP_ENTRYwr(LZCNT, G,v, E,v, zextT0), /* 0xf3 */
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X86_OP_ENTRY3(BSR, G,v, E,v, 2op,v, zextT0), /* 0xf2 */
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};
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if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
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*entry = opcodes_0FBD[0];
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} else {
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*entry = *decode_by_prefix(s, opcodes_0FBD);
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}
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}
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static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry movq[4] = {
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@ -1255,8 +1299,11 @@ static const X86OpEntry opcodes_0F[256] = {
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*/
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[0xaf] = X86_OP_ENTRY3(IMUL3, G,v, E,v, 2op,v, sextT0),
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[0xb8] = X86_OP_GROUP0(0FB8),
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/* decoded as modrm, which is visible as a difference between page fault and #UD */
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[0xb9] = X86_OP_ENTRYr(UD, nop,v), /* UD1 */
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[0xbc] = X86_OP_GROUP0(0FBC),
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[0xbd] = X86_OP_GROUP0(0FBD),
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[0xbe] = X86_OP_ENTRY3(MOV, G,v, E,b, None, None, sextT0), /* MOVSX */
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[0xbf] = X86_OP_ENTRY3(MOV, G,v, E,w, None, None, sextT0), /* MOVSX */
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@ -2158,6 +2205,8 @@ static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
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return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
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case X86_FEAT_PCLMULQDQ:
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return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
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case X86_FEAT_POPCNT:
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return (s->cpuid_ext_features & CPUID_EXT_POPCNT);
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case X86_FEAT_SSE:
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return (s->cpuid_features & CPUID_SSE);
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case X86_FEAT_SSE2:
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@ -2548,8 +2597,7 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
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case 0xab: /* bts */
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case 0xb0 ... 0xb1: /* cmpxchg */
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case 0xb3: /* btr */
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case 0xb8: /* integer ops */
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case 0xba ... 0xbd: /* integer ops */
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case 0xba ... 0xbb: /* grp8, btc */
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case 0xc0 ... 0xc1: /* xadd */
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case 0xc7: /* grp9 */
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disas_insn_old(s, cpu, b + 0x100);
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@ -120,6 +120,7 @@ typedef enum X86CPUIDFeature {
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X86_FEAT_FXSR,
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X86_FEAT_MOVBE,
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X86_FEAT_PCLMULQDQ,
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X86_FEAT_POPCNT,
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X86_FEAT_SHA_NI,
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X86_FEAT_SSE,
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X86_FEAT_SSE2,
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@ -1333,6 +1333,47 @@ static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode)
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}
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}
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/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */
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static void gen_BSF(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[0].ot;
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/* Only the Z bit is defined and it is related to the input. */
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decode->cc_dst = tcg_temp_new();
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decode->cc_op = CC_OP_LOGICB + ot;
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tcg_gen_mov_tl(decode->cc_dst, s->T0);
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/*
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* The manual says that the output is undefined when the
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* input is zero, but real hardware leaves it unchanged, and
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* real programs appear to depend on that. Accomplish this
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* by passing the output as the value to return upon zero.
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*/
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tcg_gen_ctz_tl(s->T0, s->T0, s->T1);
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}
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/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */
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static void gen_BSR(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[0].ot;
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/* Only the Z bit is defined and it is related to the input. */
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decode->cc_dst = tcg_temp_new();
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decode->cc_op = CC_OP_LOGICB + ot;
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tcg_gen_mov_tl(decode->cc_dst, s->T0);
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/*
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* The manual says that the output is undefined when the
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* input is zero, but real hardware leaves it unchanged, and
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* real programs appear to depend on that. Accomplish this
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* by passing the output as the value to return upon zero.
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* Plus, return the bit index of the first 1 bit.
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*/
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tcg_gen_xori_tl(s->T1, s->T1, TARGET_LONG_BITS - 1);
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tcg_gen_clz_tl(s->T0, s->T0, s->T1);
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tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1);
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}
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static void gen_BSWAP(DisasContext *s, X86DecodedInsn *decode)
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{
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#ifdef TARGET_X86_64
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@ -2134,6 +2175,24 @@ static void gen_LSS(DisasContext *s, X86DecodedInsn *decode)
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gen_lxx_seg(s, decode, R_SS);
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}
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static void gen_LZCNT(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[0].ot;
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/* C bit (cc_src) is defined related to the input. */
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decode->cc_src = tcg_temp_new();
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decode->cc_dst = s->T0;
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decode->cc_op = CC_OP_BMILGB + ot;
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tcg_gen_mov_tl(decode->cc_src, s->T0);
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/*
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* Reduce the target_ulong result by the number of zeros that
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* we expect to find at the top.
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*/
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tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS);
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tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - (8 << ot));
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}
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static void gen_MFENCE(DisasContext *s, X86DecodedInsn *decode)
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{
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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@ -2692,6 +2751,15 @@ static void gen_POPA(DisasContext *s, X86DecodedInsn *decode)
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gen_popa(s);
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}
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static void gen_POPCNT(DisasContext *s, X86DecodedInsn *decode)
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{
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decode->cc_src = tcg_temp_new();
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decode->cc_op = CC_OP_POPCNT;
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tcg_gen_mov_tl(decode->cc_src, s->T0);
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tcg_gen_ctpop_tl(s->T0, s->T0);
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}
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static void gen_POPF(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot;
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@ -3773,6 +3841,20 @@ static void gen_SYSRET(DisasContext *s, X86DecodedInsn *decode)
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s->base.is_jmp = DISAS_EOB_RECHECK_TF;
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}
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static void gen_TZCNT(DisasContext *s, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[0].ot;
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/* C bit (cc_src) is defined related to the input. */
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decode->cc_src = tcg_temp_new();
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decode->cc_dst = s->T0;
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decode->cc_op = CC_OP_BMILGB + ot;
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tcg_gen_mov_tl(decode->cc_src, s->T0);
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/* A zero input returns the operand size. */
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tcg_gen_ctzi_tl(s->T0, s->T0, 8 << ot);
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}
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static void gen_UD(DisasContext *s, X86DecodedInsn *decode)
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{
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gen_illegal_opcode(s);
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@ -823,11 +823,6 @@ static void gen_movs(DisasContext *s, MemOp ot)
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gen_op_add_reg(s, s->aflag, R_EDI, dshift);
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}
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static void gen_op_update1_cc(DisasContext *s)
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{
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tcg_gen_mov_tl(cpu_cc_dst, s->T0);
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}
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static void gen_op_update2_cc(DisasContext *s)
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{
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tcg_gen_mov_tl(cpu_cc_src, s->T1);
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@ -3311,56 +3306,6 @@ static void disas_insn_old(DisasContext *s, CPUState *cpu, int b)
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break;
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}
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break;
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case 0x1bc: /* bsf / tzcnt */
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case 0x1bd: /* bsr / lzcnt */
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ot = dflag;
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modrm = x86_ldub_code(env, s);
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reg = ((modrm >> 3) & 7) | REX_R(s);
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gen_ld_modrm(env, s, modrm, ot);
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gen_extu(ot, s->T0);
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/* Note that lzcnt and tzcnt are in different extensions. */
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if ((prefixes & PREFIX_REPZ)
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&& (b & 1
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? s->cpuid_ext3_features & CPUID_EXT3_ABM
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: s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
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int size = 8 << ot;
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/* For lzcnt/tzcnt, C bit is defined related to the input. */
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tcg_gen_mov_tl(cpu_cc_src, s->T0);
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if (b & 1) {
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/* For lzcnt, reduce the target_ulong result by the
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number of zeros that we expect to find at the top. */
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tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS);
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tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - size);
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} else {
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/* For tzcnt, a zero input must return the operand size. */
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tcg_gen_ctzi_tl(s->T0, s->T0, size);
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}
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/* For lzcnt/tzcnt, Z bit is defined related to the result. */
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gen_op_update1_cc(s);
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set_cc_op(s, CC_OP_BMILGB + ot);
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} else {
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/* For bsr/bsf, only the Z bit is defined and it is related
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to the input and not the result. */
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tcg_gen_mov_tl(cpu_cc_dst, s->T0);
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set_cc_op(s, CC_OP_LOGICB + ot);
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/* ??? The manual says that the output is undefined when the
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input is zero, but real hardware leaves it unchanged, and
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real programs appear to depend on that. Accomplish this
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by passing the output as the value to return upon zero. */
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if (b & 1) {
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/* For bsr, return the bit index of the first 1 bit,
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not the count of leading zeros. */
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tcg_gen_xori_tl(s->T1, cpu_regs[reg], TARGET_LONG_BITS - 1);
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tcg_gen_clz_tl(s->T0, s->T0, s->T1);
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tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1);
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} else {
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tcg_gen_ctz_tl(s->T0, s->T0, cpu_regs[reg]);
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}
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}
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gen_op_mov_reg_v(s, ot, reg, s->T0);
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break;
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case 0x100:
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modrm = x86_ldub_code(env, s);
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mod = (modrm >> 6) & 3;
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@ -3955,25 +3900,6 @@ static void disas_insn_old(DisasContext *s, CPUState *cpu, int b)
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}
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gen_nop_modrm(env, s, modrm);
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break;
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case 0x1b8: /* SSE4.2 popcnt */
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if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
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PREFIX_REPZ)
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goto illegal_op;
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if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
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goto illegal_op;
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modrm = x86_ldub_code(env, s);
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reg = ((modrm >> 3) & 7) | REX_R(s);
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ot = dflag;
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gen_ld_modrm(env, s, modrm, ot);
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gen_extu(ot, s->T0);
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tcg_gen_mov_tl(cpu_cc_src, s->T0);
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tcg_gen_ctpop_tl(s->T0, s->T0);
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gen_op_mov_reg_v(s, ot, reg, s->T0);
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set_cc_op(s, CC_OP_POPCNT);
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break;
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default:
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g_assert_not_reached();
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}
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