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target/arm: Only implement doubles if the FPU supports them

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The architecture permits FPUs which have only single-precision
support, not double-precision; Cortex-M4 and Cortex-M33 are
both like that. Add the necessary checks on the MVFR0 FPDP
field so that we UNDEF any double-precision instructions on
CPUs like this.

Note that even if FPDP==0 the insns like VMOV-to/from-gpreg,
VLDM/VSTM, VLDR/VSTR which take double precision registers
still exist.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190614104457.24703-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-06-14 11:44:57 +01:00
parent 83655223ac
commit 1120827fa1
2 changed files with 90 additions and 0 deletions
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6
target/arm/cpu.h
View File

@ -3388,6 +3388,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point */
return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
}
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so

84
target/arm/translate-vfp.inc.c
View File

@ -206,6 +206,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
@ -334,6 +339,11 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
@ -415,6 +425,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
((a->vm | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rm = a->vm;
@ -473,6 +488,11 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rm = a->vm;
@ -1301,6 +1321,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@ -1446,6 +1470,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@ -1743,6 +1771,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -1901,6 +1933,10 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@ -2041,6 +2077,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2110,6 +2150,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2172,6 +2216,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2228,6 +2276,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2285,6 +2337,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2340,6 +2396,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2364,6 +2424,10 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2388,6 +2452,10 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2438,6 +2506,10 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2474,6 +2546,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2563,6 +2639,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2655,6 +2735,10 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}