target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3223,36 +3223,14 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
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for (xs = 0; xs < selem; xs++) {
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if (replicate) {
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/* Load and replicate to all elements */
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uint64_t mulconst;
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
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get_mem_index(s), s->be_data + scale);
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switch (scale) {
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case 0:
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mulconst = 0x0101010101010101ULL;
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break;
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case 1:
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mulconst = 0x0001000100010001ULL;
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break;
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case 2:
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mulconst = 0x0000000100000001ULL;
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break;
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case 3:
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mulconst = 0;
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break;
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default:
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g_assert_not_reached();
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}
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if (mulconst) {
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tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
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}
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write_vec_element(s, tcg_tmp, rt, 0, MO_64);
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if (is_q) {
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write_vec_element(s, tcg_tmp, rt, 1, MO_64);
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}
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tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
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(is_q + 1) * 8, vec_full_reg_size(s),
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tcg_tmp);
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tcg_temp_free_i64(tcg_tmp);
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clear_vec_high(s, is_q, rt);
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} else {
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/* Load/store one element per register */
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if (is_load) {
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