hw/riscv: virt: Re-factor FDT generation
We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-4-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
b8fb878aa2
commit
0ffc1a9522
517
hw/riscv/virt.c
517
hw/riscv/virt.c
@ -176,214 +176,262 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
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0x1800, 0, 0, 0x7);
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}
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static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
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uint64_t mem_size, const char *cmdline, bool is_32_bit)
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static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
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char *clust_name, uint32_t *phandle,
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bool is_32_bit, uint32_t *intc_phandles)
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{
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void *fdt;
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int i, cpu, socket;
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int cpu;
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uint32_t cpu_phandle;
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MachineState *mc = MACHINE(s);
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char *name, *cpu_name, *core_name, *intc_name;
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = (*phandle)++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(mc->fdt, cpu_name);
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qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
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(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
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intc_phandles[cpu] = (*phandle)++;
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(mc->fdt, intc_name);
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qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
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intc_phandles[cpu]);
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qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(mc->fdt, core_name);
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qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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}
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static void create_fdt_socket_memory(RISCVVirtState *s,
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const MemMapEntry *memmap, int socket)
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{
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char *mem_name;
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uint64_t addr, size;
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uint32_t *clint_cells, *plic_cells;
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unsigned long clint_addr, plic_addr;
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uint32_t plic_phandle[MAX_NODES];
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uint32_t cpu_phandle, intc_phandle, test_phandle;
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uint32_t phandle = 1, plic_mmio_phandle = 1;
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uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
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char *mem_name, *cpu_name, *core_name, *intc_name;
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char *name, *clint_name, *plic_name, *clust_name;
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hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
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hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
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MachineState *mc = MACHINE(s);
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addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(mc->fdt, mem_name);
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qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
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g_free(mem_name);
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}
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static void create_fdt_socket_clint(RISCVVirtState *s,
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const MemMapEntry *memmap, int socket,
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uint32_t *intc_phandles)
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{
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int cpu;
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char *clint_name;
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uint32_t *clint_cells;
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unsigned long clint_addr;
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MachineState *mc = MACHINE(s);
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static const char * const clint_compat[2] = {
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"sifive,clint0", "riscv,clint0"
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};
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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}
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clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(mc->fdt, clint_name);
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qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
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(char **)&clint_compat,
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ARRAY_SIZE(clint_compat));
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qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
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g_free(clint_name);
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g_free(clint_cells);
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}
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static void create_fdt_socket_plic(RISCVVirtState *s,
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const MemMapEntry *memmap, int socket,
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uint32_t *phandle, uint32_t *intc_phandles,
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uint32_t *plic_phandles)
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{
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int cpu;
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char *plic_name;
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uint32_t *plic_cells;
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unsigned long plic_addr;
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MachineState *mc = MACHINE(s);
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static const char * const plic_compat[2] = {
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"sifive,plic-1.0.0", "riscv,plic0"
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};
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if (mc->dtb) {
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fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
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if (!fdt) {
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error_report("load_device_tree() failed");
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exit(1);
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}
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goto update_bootargs;
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} else {
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fdt = mc->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
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plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
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plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
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plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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plic_phandles[socket] = (*phandle)++;
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plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
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plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
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qemu_fdt_add_subnode(mc->fdt, plic_name);
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qemu_fdt_setprop_cell(mc->fdt, plic_name,
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"#address-cells", FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(mc->fdt, plic_name,
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"#interrupt-cells", FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
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(char **)&plic_compat,
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ARRAY_SIZE(plic_compat));
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qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
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plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
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0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
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riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
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qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
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plic_phandles[socket]);
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g_free(plic_name);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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g_free(plic_cells);
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}
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
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bool is_32_bit, uint32_t *phandle,
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uint32_t *irq_mmio_phandle,
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uint32_t *irq_pcie_phandle,
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uint32_t *irq_virtio_phandle)
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{
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int socket;
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char *clust_name;
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uint32_t *intc_phandles;
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MachineState *mc = MACHINE(s);
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uint32_t xplic_phandles[MAX_NODES];
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qemu_fdt_add_subnode(mc->fdt, "/cpus");
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qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
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RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
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for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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qemu_fdt_add_subnode(mc->fdt, clust_name);
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plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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create_fdt_socket_cpus(s, socket, clust_name, phandle,
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is_32_bit, intc_phandles);
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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if (is_32_bit) {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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} else {
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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}
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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create_fdt_socket_memory(s, memmap, socket);
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(fdt, intc_name);
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intc_phandle = phandle++;
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qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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create_fdt_socket_clint(s, memmap, socket, intc_phandles);
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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create_fdt_socket_plic(s, memmap, socket, phandle,
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intc_phandles, xplic_phandles);
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plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(fdt, core_name);
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qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(fdt, mem_name);
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qemu_fdt_setprop_cells(fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
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g_free(mem_name);
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clint_addr = memmap[VIRT_CLINT].base +
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(memmap[VIRT_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(fdt, clint_name);
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qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
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(char **)&clint_compat, ARRAY_SIZE(clint_compat));
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qemu_fdt_setprop_cells(fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
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g_free(clint_name);
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plic_phandle[socket] = phandle++;
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plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
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plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
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qemu_fdt_add_subnode(fdt, plic_name);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#address-cells", FDT_PLIC_ADDR_CELLS);
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qemu_fdt_setprop_cell(fdt, plic_name,
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"#interrupt-cells", FDT_PLIC_INT_CELLS);
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qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
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(char **)&plic_compat, ARRAY_SIZE(plic_compat));
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qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
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plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, plic_name, "reg",
|
||||
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
|
||||
qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
|
||||
riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
|
||||
qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
|
||||
g_free(plic_name);
|
||||
|
||||
g_free(clint_cells);
|
||||
g_free(plic_cells);
|
||||
g_free(intc_phandles);
|
||||
g_free(clust_name);
|
||||
}
|
||||
|
||||
for (socket = 0; socket < riscv_socket_count(mc); socket++) {
|
||||
if (socket == 0) {
|
||||
plic_mmio_phandle = plic_phandle[socket];
|
||||
plic_virtio_phandle = plic_phandle[socket];
|
||||
plic_pcie_phandle = plic_phandle[socket];
|
||||
*irq_mmio_phandle = xplic_phandles[socket];
|
||||
*irq_virtio_phandle = xplic_phandles[socket];
|
||||
*irq_pcie_phandle = xplic_phandles[socket];
|
||||
}
|
||||
if (socket == 1) {
|
||||
plic_virtio_phandle = plic_phandle[socket];
|
||||
plic_pcie_phandle = plic_phandle[socket];
|
||||
*irq_virtio_phandle = xplic_phandles[socket];
|
||||
*irq_pcie_phandle = xplic_phandles[socket];
|
||||
}
|
||||
if (socket == 2) {
|
||||
plic_pcie_phandle = plic_phandle[socket];
|
||||
*irq_pcie_phandle = xplic_phandles[socket];
|
||||
}
|
||||
}
|
||||
|
||||
riscv_socket_fdt_write_distance_matrix(mc, fdt);
|
||||
riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
|
||||
}
|
||||
|
||||
static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint32_t irq_virtio_phandle)
|
||||
{
|
||||
int i;
|
||||
char *name;
|
||||
MachineState *mc = MACHINE(s);
|
||||
|
||||
for (i = 0; i < VIRTIO_COUNT; i++) {
|
||||
name = g_strdup_printf("/soc/virtio_mmio@%lx",
|
||||
(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
|
||||
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
|
||||
0x0, memmap[VIRT_VIRTIO].size);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
|
||||
plic_virtio_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
|
||||
irq_virtio_phandle);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
|
||||
g_free(name);
|
||||
}
|
||||
}
|
||||
|
||||
static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint32_t irq_pcie_phandle)
|
||||
{
|
||||
char *name;
|
||||
MachineState *mc = MACHINE(s);
|
||||
|
||||
name = g_strdup_printf("/soc/pci@%lx",
|
||||
(long) memmap[VIRT_PCIE_ECAM].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
|
||||
qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
|
||||
qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
|
||||
qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
|
||||
qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
|
||||
FDT_PCI_ADDR_CELLS);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
|
||||
FDT_PCI_INT_CELLS);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible",
|
||||
"pci-host-ecam-generic");
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
|
||||
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
|
||||
qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg", 0,
|
||||
qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
|
||||
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
|
||||
qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
|
||||
qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
|
||||
1, FDT_PCI_RANGE_IOPORT, 2, 0,
|
||||
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
|
||||
1, FDT_PCI_RANGE_MMIO,
|
||||
@ -393,66 +441,96 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
2, virt_high_pcie_memmap.base,
|
||||
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
|
||||
|
||||
create_pcie_irq_map(fdt, name, plic_pcie_phandle);
|
||||
create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
test_phandle = phandle++;
|
||||
static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint32_t *phandle)
|
||||
{
|
||||
char *name;
|
||||
uint32_t test_phandle;
|
||||
MachineState *mc = MACHINE(s);
|
||||
|
||||
test_phandle = (*phandle)++;
|
||||
name = g_strdup_printf("/soc/test@%lx",
|
||||
(long)memmap[VIRT_TEST].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
{
|
||||
static const char * const compat[3] = {
|
||||
"sifive,test1", "sifive,test0", "syscon"
|
||||
};
|
||||
qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
|
||||
ARRAY_SIZE(compat));
|
||||
qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
|
||||
(char **)&compat, ARRAY_SIZE(compat));
|
||||
}
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
0x0, memmap[VIRT_TEST].base,
|
||||
0x0, memmap[VIRT_TEST].size);
|
||||
qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
|
||||
test_phandle = qemu_fdt_get_phandle(fdt, name);
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
|
||||
0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
|
||||
test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
|
||||
g_free(name);
|
||||
|
||||
name = g_strdup_printf("/soc/reboot");
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
|
||||
qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
|
||||
g_free(name);
|
||||
|
||||
name = g_strdup_printf("/soc/poweroff");
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
|
||||
qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint32_t irq_mmio_phandle)
|
||||
{
|
||||
char *name;
|
||||
MachineState *mc = MACHINE(s);
|
||||
|
||||
name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
|
||||
0x0, memmap[VIRT_UART0].base,
|
||||
0x0, memmap[VIRT_UART0].size);
|
||||
qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/chosen");
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
|
||||
qemu_fdt_add_subnode(mc->fdt, "/chosen");
|
||||
qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint32_t irq_mmio_phandle)
|
||||
{
|
||||
char *name;
|
||||
MachineState *mc = MACHINE(s);
|
||||
|
||||
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
|
||||
qemu_fdt_add_subnode(fdt, name);
|
||||
qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
|
||||
qemu_fdt_setprop_cells(fdt, name, "reg",
|
||||
0x0, memmap[VIRT_RTC].base,
|
||||
0x0, memmap[VIRT_RTC].size);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
qemu_fdt_setprop_string(mc->fdt, name, "compatible",
|
||||
"google,goldfish-rtc");
|
||||
qemu_fdt_setprop_cells(mc->fdt, name, "reg",
|
||||
0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
|
||||
irq_mmio_phandle);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
|
||||
{
|
||||
char *name;
|
||||
MachineState *mc = MACHINE(s);
|
||||
hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
|
||||
hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
|
||||
|
||||
name = g_strdup_printf("/flash@%" PRIx64, flashbase);
|
||||
qemu_fdt_add_subnode(mc->fdt, name);
|
||||
@ -462,10 +540,59 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
2, flashbase + flashsize, 2, flashsize);
|
||||
qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
|
||||
g_free(name);
|
||||
}
|
||||
|
||||
static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
|
||||
uint64_t mem_size, const char *cmdline, bool is_32_bit)
|
||||
{
|
||||
MachineState *mc = MACHINE(s);
|
||||
uint32_t phandle = 1, irq_mmio_phandle = 1;
|
||||
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
|
||||
|
||||
if (mc->dtb) {
|
||||
mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
|
||||
if (!mc->fdt) {
|
||||
error_report("load_device_tree() failed");
|
||||
exit(1);
|
||||
}
|
||||
goto update_bootargs;
|
||||
} else {
|
||||
mc->fdt = create_device_tree(&s->fdt_size);
|
||||
if (!mc->fdt) {
|
||||
error_report("create_device_tree() failed");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
|
||||
qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
|
||||
qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
|
||||
|
||||
qemu_fdt_add_subnode(mc->fdt, "/soc");
|
||||
qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
|
||||
qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
|
||||
qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
|
||||
qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
|
||||
|
||||
create_fdt_sockets(s, memmap, is_32_bit, &phandle,
|
||||
&irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
|
||||
|
||||
create_fdt_virtio(s, memmap, irq_virtio_phandle);
|
||||
|
||||
create_fdt_pcie(s, memmap, irq_pcie_phandle);
|
||||
|
||||
create_fdt_reset(s, memmap, &phandle);
|
||||
|
||||
create_fdt_uart(s, memmap, irq_mmio_phandle);
|
||||
|
||||
create_fdt_rtc(s, memmap, irq_mmio_phandle);
|
||||
|
||||
create_fdt_flash(s, memmap);
|
||||
|
||||
update_bootargs:
|
||||
if (cmdline) {
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||||
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user