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target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

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If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 93cb52b7a3ccc64e8d28813324818edae07e21d5)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Max Chou 2024-03-22 17:25:58 +08:00 committed by Michael Tokarev
parent c4173e4caf
commit 0f9578497c
1 changed files with 4 additions and 12 deletions
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16
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2381,7 +2381,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
}
@ -2424,7 +2423,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
@ -2457,7 +2455,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
}
@ -2500,7 +2497,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dd(s, a->rd, a->rs2, a->vm);
}
@ -2766,8 +2762,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
require_scale_rvfmin(s);
}
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
@ -2878,16 +2873,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
require_scale_rvfmin(s);
}
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8);
require_scale_rvf(s);
}
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
@ -3021,8 +3014,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_widen_check(s, a) &&
require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8);
require_scale_rvf(s);
}
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)