target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -98,6 +98,9 @@ libobj-$(TARGET_CRIS) += cpu.o
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libobj-$(TARGET_LM32) += cpu.o
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libobj-$(TARGET_LM32) += cpu.o
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libobj-$(TARGET_M68K) += cpu.o
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libobj-$(TARGET_M68K) += cpu.o
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libobj-$(TARGET_MICROBLAZE) += cpu.o
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libobj-$(TARGET_MICROBLAZE) += cpu.o
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ifeq ($(TARGET_BASE_ARCH), mips)
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libobj-y += cpu.o
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endif
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libobj-$(TARGET_S390X) += cpu.o
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libobj-$(TARGET_S390X) += cpu.o
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libobj-$(TARGET_SH4) += cpu.o
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libobj-$(TARGET_SH4) += cpu.o
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ifeq ($(TARGET_BASE_ARCH), sparc)
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ifeq ($(TARGET_BASE_ARCH), sparc)
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74
target-mips/cpu-qom.h
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74
target-mips/cpu-qom.h
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@ -0,0 +1,74 @@
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/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_MIPS_CPU_QOM_H
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#define QEMU_MIPS_CPU_QOM_H
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#include "qemu/cpu.h"
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#ifdef TARGET_MIPS64
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#define TYPE_MIPS_CPU "mips64-cpu"
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#else
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#define TYPE_MIPS_CPU "mips-cpu"
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#endif
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#define MIPS_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
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#define MIPS_CPU(obj) \
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OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
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#define MIPS_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
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/**
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* MIPSCPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* A MIPS CPU model.
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*/
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typedef struct MIPSCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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void (*parent_reset)(CPUState *cpu);
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} MIPSCPUClass;
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/**
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* MIPSCPU:
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* @env: #CPUMIPSState
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*
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* A MIPS CPU.
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*/
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typedef struct MIPSCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUMIPSState env;
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} MIPSCPU;
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static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
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{
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return MIPS_CPU(container_of(env, MIPSCPU, env));
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}
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#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
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#endif
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60
target-mips/cpu.c
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60
target-mips/cpu.c
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@ -0,0 +1,60 @@
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/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void mips_cpu_reset(CPUState *s)
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{
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MIPSCPU *cpu = MIPS_CPU(s);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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mcc->parent_reset(s);
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cpu_state_reset(env);
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}
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static void mips_cpu_class_init(ObjectClass *c, void *data)
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{
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MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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mcc->parent_reset = cc->reset;
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cc->reset = mips_cpu_reset;
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}
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static const TypeInfo mips_cpu_type_info = {
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.name = TYPE_MIPS_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MIPSCPU),
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.abstract = false,
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.class_size = sizeof(MIPSCPUClass),
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.class_init = mips_cpu_class_init,
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};
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static void mips_cpu_register_types(void)
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{
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type_register_static(&mips_cpu_type_info);
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}
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type_init(mips_cpu_register_types)
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@ -483,6 +483,8 @@ struct CPUMIPSState {
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struct QEMUTimer *timer; /* Internal timer */
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struct QEMUTimer *timer; /* Internal timer */
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};
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};
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#include "cpu-qom.h"
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
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int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
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target_ulong address, int rw, int access_type);
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target_ulong address, int rw, int access_type);
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@ -12691,13 +12691,15 @@ static void mips_tcg_init(void)
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CPUMIPSState *cpu_mips_init (const char *cpu_model)
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CPUMIPSState *cpu_mips_init (const char *cpu_model)
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{
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{
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MIPSCPU *cpu;
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CPUMIPSState *env;
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CPUMIPSState *env;
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const mips_def_t *def;
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const mips_def_t *def;
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def = cpu_mips_find_by_name(cpu_model);
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def = cpu_mips_find_by_name(cpu_model);
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if (!def)
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if (!def)
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return NULL;
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return NULL;
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env = g_malloc0(sizeof(CPUMIPSState));
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cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
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env = &cpu->env;
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env->cpu_model = def;
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env->cpu_model = def;
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env->cpu_model_str = cpu_model;
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env->cpu_model_str = cpu_model;
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