Remove unnecessary cast when using the cpu_[physical]_memory API
This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const. Suggested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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d7ef71ef42
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@ -91,9 +91,9 @@ static void omap_update_display(void *opaque)
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frame_offset = 0;
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if (omap_lcd->plm != 2) {
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cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[
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omap_lcd->dma->current_frame],
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(void *)omap_lcd->palette, 0x200);
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cpu_physical_memory_read(
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omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame],
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omap_lcd->palette, 0x200);
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switch (omap_lcd->palette[0] >> 12 & 7) {
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case 3 ... 7:
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frame_offset += 0x200;
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@ -244,8 +244,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
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if (s->plm != 2 && !s->palette_done) {
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cpu_physical_memory_read(
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s->dma->phys_framebuffer[s->dma->current_frame],
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(void *)s->palette, 0x200);
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s->dma->phys_framebuffer[s->dma->current_frame],
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s->palette, 0x200);
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s->palette_done = 1;
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omap_lcd_interrupts(s);
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}
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@ -225,9 +225,8 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
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hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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cpu_physical_memory_read(addr, &ctrl->channels[c].current_g,
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sizeof(ctrl->channels[c].current_g));
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}
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static void dump_c(int ch, struct dma_descr_context *c)
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@ -257,9 +256,8 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
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hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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cpu_physical_memory_read(addr, &ctrl->channels[c].current_c,
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sizeof(ctrl->channels[c].current_c));
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D(dump_c(c, &ctrl->channels[c].current_c));
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/* I guess this should update the current pos. */
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@ -275,9 +273,8 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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cpu_physical_memory_read(addr, &ctrl->channels[c].current_d,
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sizeof(ctrl->channels[c].current_d));
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D(dump_d(c, &ctrl->channels[c].current_d));
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ctrl->channels[c].regs[RW_DATA] = addr;
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@ -290,9 +287,8 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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D(dump_d(c, &ctrl->channels[c].current_d));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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cpu_physical_memory_write(addr, &ctrl->channels[c].current_c,
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sizeof(ctrl->channels[c].current_c));
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}
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
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@ -301,9 +297,8 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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cpu_physical_memory_write(addr, &ctrl->channels[c].current_d,
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sizeof(ctrl->channels[c].current_d));
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}
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
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@ -404,8 +404,7 @@ pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
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cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
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trace_pvscsi_cmp_ring_put(cmp_descr_pa);
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cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
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sizeof(*cmp_desc));
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cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc));
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}
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static void
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@ -415,8 +414,7 @@ pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
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msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
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trace_pvscsi_msg_ring_put(msg_descr_pa);
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cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
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sizeof(*msg_desc));
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cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc));
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}
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static void
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@ -491,7 +489,7 @@ pvscsi_get_next_sg_elem(PVSCSISGState *sg)
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{
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struct PVSCSISGElement elem;
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cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
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cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem));
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if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
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/*
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* There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
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@ -42,6 +42,16 @@ type T;
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+ address_space_write_rom(E1, E2, E3, E4, E5)
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- cpu_physical_memory_rw(E1, (T *)(E2), E3, E4)
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+ cpu_physical_memory_rw(E1, E2, E3, E4)
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- cpu_physical_memory_read(E1, (T *)(E2), E3)
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+ cpu_physical_memory_read(E1, E2, E3)
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- cpu_physical_memory_write(E1, (T *)(E2), E3)
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+ cpu_physical_memory_write(E1, E2, E3)
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- dma_memory_read(E1, E2, (T *)(E3), E4)
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+ dma_memory_read(E1, E2, E3, E4)
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@ -367,7 +367,7 @@ static int hax_accel_init(MachineState *ms)
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static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft)
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{
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if (hft->direction < 2) {
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cpu_physical_memory_rw(hft->gpa, (uint8_t *) &hft->value, hft->size,
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cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size,
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hft->direction);
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} else {
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/*
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@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft)
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* hft->direction == 2: gpa ==> gpa2
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*/
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uint64_t value;
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cpu_physical_memory_rw(hft->gpa, (uint8_t *) &value, hft->size, 0);
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cpu_physical_memory_rw(hft->gpa2, (uint8_t *) &value, hft->size, 1);
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cpu_physical_memory_rw(hft->gpa, &value, hft->size, 0);
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cpu_physical_memory_rw(hft->gpa2, &value, hft->size, 1);
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}
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return 0;
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