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target/mips: Remove now unreachable LSA/DLSA opcodes code 

Since we switched to decodetree-generated processing,
we can remove this now unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-08 19:01:01 +01:00
parent 3f7a927847
commit 0e9524af2d
1 changed files with 5 additions and 23 deletions
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28
target/mips/translate.c
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@ -280,9 +280,6 @@ enum {
R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
R6_OPC_DCLO = 0x13 | OPC_SPECIAL, R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
OPC_LSA = 0x05 | OPC_SPECIAL,
OPC_DLSA = 0x15 | OPC_SPECIAL,
}; };
/* Multiplication variants of the vr54xx. */ /* Multiplication variants of the vr54xx. */
@ -24318,9 +24315,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode); op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_LSA:
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case OPC_MULT: case OPC_MULT:
case OPC_MULTU: case OPC_MULTU:
case OPC_DIV: case OPC_DIV:
@ -24371,9 +24365,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DLSA:
gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case R6_OPC_DCLO: case R6_OPC_DCLO:
case R6_OPC_DCLZ: case R6_OPC_DCLZ:
if (rt == 0 && sa == 1) { if (rt == 0 && sa == 1) {
@ -24635,18 +24626,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, ISA_MIPS2); check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1); gen_trap(ctx, op1, rs, rt, -1);
break; break;
case OPC_LSA: /* OPC_PMON */ case OPC_PMON:
if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { /* Pmon entry point, also R4010 selsl */
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD #ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl"); MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
#else #else
gen_helper_0e0i(pmon, sa); gen_helper_0e0i(pmon, sa);
#endif #endif
}
break; break;
case OPC_SYSCALL: case OPC_SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL); generate_exception_end(ctx, EXCP_SYSCALL);
@ -24737,11 +24724,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case OPC_DLSA:
if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;
#endif #endif
default: default:
if (ctx->insn_flags & ISA_MIPS_R6) { if (ctx->insn_flags & ISA_MIPS_R6) {