mirror of https://gitlab.com/qemu-project/qemu
target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
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@ -280,9 +280,6 @@ enum {
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R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
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R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
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R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
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R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
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R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
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R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
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OPC_LSA = 0x05 | OPC_SPECIAL,
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OPC_DLSA = 0x15 | OPC_SPECIAL,
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};
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};
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/* Multiplication variants of the vr54xx. */
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/* Multiplication variants of the vr54xx. */
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@ -24318,9 +24315,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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op1 = MASK_SPECIAL(ctx->opcode);
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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switch (op1) {
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case OPC_LSA:
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gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
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break;
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case OPC_MULT:
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case OPC_MULT:
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case OPC_MULTU:
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case OPC_MULTU:
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case OPC_DIV:
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case OPC_DIV:
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@ -24371,9 +24365,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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break;
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break;
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#if defined(TARGET_MIPS64)
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#if defined(TARGET_MIPS64)
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case OPC_DLSA:
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gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
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break;
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case R6_OPC_DCLO:
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case R6_OPC_DCLO:
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case R6_OPC_DCLZ:
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case R6_OPC_DCLZ:
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if (rt == 0 && sa == 1) {
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if (rt == 0 && sa == 1) {
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@ -24635,10 +24626,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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check_insn(ctx, ISA_MIPS2);
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check_insn(ctx, ISA_MIPS2);
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gen_trap(ctx, op1, rs, rt, -1);
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gen_trap(ctx, op1, rs, rt, -1);
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break;
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break;
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case OPC_LSA: /* OPC_PMON */
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case OPC_PMON:
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if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
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decode_opc_special_r6(env, ctx);
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} else {
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/* Pmon entry point, also R4010 selsl */
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/* Pmon entry point, also R4010 selsl */
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#ifdef MIPS_STRICT_STANDARD
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#ifdef MIPS_STRICT_STANDARD
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MIPS_INVAL("PMON / selsl");
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MIPS_INVAL("PMON / selsl");
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@ -24646,7 +24634,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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#else
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#else
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gen_helper_0e0i(pmon, sa);
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gen_helper_0e0i(pmon, sa);
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#endif
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#endif
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}
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break;
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break;
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case OPC_SYSCALL:
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case OPC_SYSCALL:
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generate_exception_end(ctx, EXCP_SYSCALL);
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generate_exception_end(ctx, EXCP_SYSCALL);
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@ -24737,11 +24724,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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break;
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break;
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}
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}
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break;
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break;
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case OPC_DLSA:
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if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
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decode_opc_special_r6(env, ctx);
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}
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break;
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#endif
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#endif
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default:
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default:
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if (ctx->insn_flags & ISA_MIPS_R6) {
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if (ctx->insn_flags & ISA_MIPS_R6) {
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