s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1
The semantics of ASI/ASGI/ALSI/ALSGI changed. Let's implement them just like LOAD AND ADD, so they are atomic. Emulate old behavior. This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -39,10 +39,10 @@
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C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
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C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
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/* ADD IMMEDIATE */
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/* ADD IMMEDIATE */
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C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32)
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C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32)
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C(0xeb6a, ASI, SIY, GIE, m1_32s, i2, new, m1_32, add, adds32)
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D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL)
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C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32)
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C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32)
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C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
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C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
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C(0xeb7a, AGSI, SIY, GIE, m1_64, i2, new, m1_64, add, adds64)
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D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEQ)
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C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64)
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C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64)
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/* ADD IMMEDIATE HIGH */
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/* ADD IMMEDIATE HIGH */
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C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
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C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
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@ -70,9 +70,9 @@
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C(0xc20b, ALFI, RIL_a, EI, r1, i2_32u, new, r1_32, add, addu32)
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C(0xc20b, ALFI, RIL_a, EI, r1, i2_32u, new, r1_32, add, addu32)
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C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, add, addu64)
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C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, add, addu64)
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/* ADD LOGICAL WITH SIGNED IMMEDIATE */
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/* ADD LOGICAL WITH SIGNED IMMEDIATE */
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C(0xeb6e, ALSI, SIY, GIE, m1_32u, i2, new, m1_32, add, addu32)
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D(0xeb6e, ALSI, SIY, GIE, la1, i2, new, 0, asi, addu32, MO_TEUL)
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C(0xecda, ALHSIK, RIE_d, DO, r3, i2, new, r1_32, add, addu32)
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C(0xecda, ALHSIK, RIE_d, DO, r3, i2, new, r1_32, add, addu32)
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C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
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D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asi, addu64, MO_TEQ)
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C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
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C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
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/* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */
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/* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */
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C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, addu32)
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C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, addu32)
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@ -1364,6 +1364,27 @@ static ExitStatus op_addc(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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return NO_EXIT;
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}
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}
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static ExitStatus op_asi(DisasContext *s, DisasOps *o)
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{
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o->in1 = tcg_temp_new_i64();
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if (!s390_has_feat(S390_FEAT_STFLE_45)) {
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tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
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} else {
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/* Perform the atomic addition in memory. */
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tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
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s->insn->data);
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}
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/* Recompute also for atomic case: needed for setting CC. */
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tcg_gen_add_i64(o->out, o->in1, o->in2);
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if (!s390_has_feat(S390_FEAT_STFLE_45)) {
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tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
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}
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return NO_EXIT;
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}
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static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
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static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
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{
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{
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gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
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gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
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