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target/ppc: Remove MSR_SA and MSR_AP from hflags

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Nothing within the translator -- or anywhere else for that
matter -- checks MSR_SA or MSR_AP on the 602.  This may be
a mistake.  However, for the moment, we need not record these
bits in hflags.

This allows us to simplify HFLAGS_VSX computation by moving
it to overlap with MSR_VSX.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-8-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2021-03-23 12:43:37 -06:00 committed by David Gibson
parent f03de3b44b
commit 0e6bac3edb
2 changed files with 5 additions and 9 deletions
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4
target/ppc/cpu.h
View File

@ -600,14 +600,12 @@ enum {
HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_DR = 4, /* MSR_DR */
HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_IR = 5, /* MSR_IR */
HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */
HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_TM = 8, /* computed from MSR_TM */
HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_FP = 13, /* MSR_FP */
HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_PR = 14, /* MSR_PR */
HFLAGS_SA = 22, /* MSR_SA */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_AP = 23, /* MSR_AP */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
}; };

10
target/ppc/helper_regs.c
View File

@ -99,11 +99,8 @@ void hreg_compute_hflags(CPUPPCState *env)
QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR);
QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA);
QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP);
msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
(1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP));
(1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP));
if (ppc_flags & POWERPC_FLAG_HID0_LE) { if (ppc_flags & POWERPC_FLAG_HID0_LE) {
/* /*
@ -143,8 +140,9 @@ void hreg_compute_hflags(CPUPPCState *env)
QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
msr_mask |= 1 << MSR_VR; msr_mask |= 1 << MSR_VR;
} }
if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { if (ppc_flags & POWERPC_FLAG_VSX) {
hflags |= 1 << HFLAGS_VSX; QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
msr_mask |= 1 << MSR_VSX;
} }
if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
hflags |= 1 << HFLAGS_TM; hflags |= 1 << HFLAGS_TM;