util: Add cpuinfo-aarch64.c
Move the code from tcg/. The only use of these bits so far is with respect to the atomicity of tcg operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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host/include/aarch64/host/cpuinfo.h
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22
host/include/aarch64/host/cpuinfo.h
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@ -0,0 +1,22 @@
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Host specific cpu indentification for AArch64.
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*/
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#ifndef HOST_CPUINFO_H
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#define HOST_CPUINFO_H
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#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
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#define CPUINFO_LSE (1u << 1)
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#define CPUINFO_LSE2 (1u << 2)
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/* Initialized with a constructor. */
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extern unsigned cpuinfo;
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/*
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* We cannot rely on constructor ordering, so other constructors must
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* use the function interface rather than the variable above.
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*/
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unsigned cpuinfo_init(void);
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#endif /* HOST_CPUINFO_H */
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@ -13,12 +13,6 @@
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#include "../tcg-ldst.c.inc"
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#include "../tcg-ldst.c.inc"
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#include "../tcg-pool.c.inc"
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#include "../tcg-pool.c.inc"
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#include "qemu/bitops.h"
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#include "qemu/bitops.h"
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#ifdef __linux__
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#include <asm/hwcap.h>
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#endif
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#ifdef CONFIG_DARWIN
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#include <sys/sysctl.h>
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#endif
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/* We're going to re-use TCGType in setting of the SF bit, which controls
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/* We're going to re-use TCGType in setting of the SF bit, which controls
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the size of the operation performed. If we know the values match, it
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the size of the operation performed. If we know the values match, it
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@ -77,9 +71,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
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return TCG_REG_X0 + slot;
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return TCG_REG_X0 + slot;
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}
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}
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bool have_lse;
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bool have_lse2;
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#define TCG_REG_TMP TCG_REG_X30
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#define TCG_REG_TMP TCG_REG_X30
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#define TCG_VEC_TMP TCG_REG_V31
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#define TCG_VEC_TMP TCG_REG_V31
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@ -2878,39 +2869,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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}
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}
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}
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}
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#ifdef CONFIG_DARWIN
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static bool sysctl_for_bool(const char *name)
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{
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int val = 0;
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size_t len = sizeof(val);
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if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
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return val != 0;
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}
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/*
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* We might in the future ask for properties not present in older kernels,
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* but we're only asking about static properties, all of which should be
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* 'int'. So we shouln't see ENOMEM (val too small), or any of the other
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* more exotic errors.
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*/
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assert(errno == ENOENT);
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return false;
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}
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#endif
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static void tcg_target_init(TCGContext *s)
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static void tcg_target_init(TCGContext *s)
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{
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{
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#ifdef __linux__
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unsigned long hwcap = qemu_getauxval(AT_HWCAP);
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have_lse = hwcap & HWCAP_ATOMICS;
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have_lse2 = hwcap & HWCAP_USCAT;
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#endif
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#ifdef CONFIG_DARWIN
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have_lse = sysctl_for_bool("hw.optional.arm.FEAT_LSE");
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have_lse2 = sysctl_for_bool("hw.optional.arm.FEAT_LSE2");
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#endif
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
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tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
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tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
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@ -13,6 +13,8 @@
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#ifndef AARCH64_TCG_TARGET_H
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#ifndef AARCH64_TCG_TARGET_H
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#define AARCH64_TCG_TARGET_H
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#define AARCH64_TCG_TARGET_H
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#include "host/cpuinfo.h"
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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@ -57,8 +59,8 @@ typedef enum {
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#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
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#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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extern bool have_lse;
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#define have_lse (cpuinfo & CPUINFO_LSE)
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extern bool have_lse2;
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#define have_lse2 (cpuinfo & CPUINFO_LSE2)
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/* optional instructions */
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_div_i32 1
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67
util/cpuinfo-aarch64.c
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67
util/cpuinfo-aarch64.c
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Host specific cpu indentification for AArch64.
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*/
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#include "qemu/osdep.h"
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#include "host/cpuinfo.h"
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#ifdef CONFIG_LINUX
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# ifdef CONFIG_GETAUXVAL
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# include <sys/auxv.h>
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# else
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# include <asm/hwcap.h>
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# include "elf.h"
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# endif
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#endif
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#ifdef CONFIG_DARWIN
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# include <sys/sysctl.h>
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#endif
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unsigned cpuinfo;
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#ifdef CONFIG_DARWIN
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static bool sysctl_for_bool(const char *name)
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{
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int val = 0;
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size_t len = sizeof(val);
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if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
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return val != 0;
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}
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/*
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* We might in the future ask for properties not present in older kernels,
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* but we're only asking about static properties, all of which should be
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* 'int'. So we shouln't see ENOMEM (val too small), or any of the other
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* more exotic errors.
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*/
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assert(errno == ENOENT);
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return false;
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}
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#endif
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/* Called both as constructor and (possibly) via other constructors. */
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unsigned __attribute__((constructor)) cpuinfo_init(void)
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{
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unsigned info = cpuinfo;
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if (info) {
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return info;
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}
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info = CPUINFO_ALWAYS;
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#ifdef CONFIG_LINUX
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unsigned long hwcap = qemu_getauxval(AT_HWCAP);
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info |= (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0);
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info |= (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0);
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#endif
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#ifdef CONFIG_DARWIN
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info |= sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE;
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info |= sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2;
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#endif
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cpuinfo = info;
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return info;
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}
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@ -109,6 +109,8 @@ if have_block
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util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c'))
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util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c'))
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endif
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endif
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if cpu in ['x86', 'x86_64']
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if cpu == 'aarch64'
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util_ss.add(files('cpuinfo-aarch64.c'))
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elif cpu in ['x86', 'x86_64']
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util_ss.add(files('cpuinfo-i386.c'))
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util_ss.add(files('cpuinfo-i386.c'))
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endif
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endif
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