ide/ich: QOM parent field cleanup
Replace direct uses of AHCIPCIState::card with QOM casts and rename it to parent_obj. Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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fd58922cf4
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0d3aea5603
@ -117,12 +117,13 @@ static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
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static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
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static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
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{
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{
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struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
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AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
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PCIDevice *pci_dev = PCI_DEVICE(d);
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DPRINTF(0, "raise irq\n");
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DPRINTF(0, "raise irq\n");
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if (msi_enabled(&d->card)) {
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if (msi_enabled(pci_dev)) {
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msi_notify(&d->card, 0);
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msi_notify(pci_dev, 0);
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} else {
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} else {
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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}
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}
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@ -130,11 +131,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
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static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
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static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
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{
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{
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struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
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AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
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DPRINTF(0, "lower irq\n");
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DPRINTF(0, "lower irq\n");
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if (!msi_enabled(&d->card)) {
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if (!msi_enabled(PCI_DEVICE(d))) {
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qemu_irq_lower(s->irq);
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qemu_irq_lower(s->irq);
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}
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}
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}
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}
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@ -301,7 +301,10 @@ typedef struct AHCIState {
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} AHCIState;
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} AHCIState;
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typedef struct AHCIPCIState {
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typedef struct AHCIPCIState {
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PCIDevice card;
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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AHCIState ahci;
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AHCIState ahci;
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} AHCIPCIState;
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} AHCIPCIState;
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22
hw/ide/ich.c
22
hw/ide/ich.c
@ -84,7 +84,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
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.unmigratable = 1, /* Still buggy under I/O load */
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.unmigratable = 1, /* Still buggy under I/O load */
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.version_id = 1,
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.version_id = 1,
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.fields = (VMStateField []) {
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(card, AHCIPCIState),
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VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
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VMSTATE_AHCI(ahci, AHCIPCIState),
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VMSTATE_AHCI(ahci, AHCIPCIState),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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},
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},
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@ -106,30 +106,30 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
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ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
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ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
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pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
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pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
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d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
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dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
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d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
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dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
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pci_config_set_interrupt_pin(d->card.config, 1);
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pci_config_set_interrupt_pin(dev->config, 1);
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/* XXX Software should program this register */
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/* XXX Software should program this register */
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d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
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dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
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msi_init(dev, 0x50, 1, true, false);
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msi_init(dev, 0x50, 1, true, false);
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d->ahci.irq = d->card.irq[0];
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d->ahci.irq = dev->irq[0];
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pci_register_bar(&d->card, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
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pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
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&d->ahci.idp);
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&d->ahci.idp);
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pci_register_bar(&d->card, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
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pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
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&d->ahci.mem);
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&d->ahci.mem);
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sata_cap_offset = pci_add_capability(&d->card, PCI_CAP_ID_SATA,
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sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
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ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
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ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
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if (sata_cap_offset < 0) {
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if (sata_cap_offset < 0) {
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return sata_cap_offset;
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return sata_cap_offset;
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}
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}
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sata_cap = d->card.config + sata_cap_offset;
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sata_cap = dev->config + sata_cap_offset;
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pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
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pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
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pci_set_long(sata_cap + SATA_CAP_BAR,
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pci_set_long(sata_cap + SATA_CAP_BAR,
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(ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
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(ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
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