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ppc4xx_pci: Declare as little endian

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This patch replaces explicit bswaps with endianness hints to the
mmio layer.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Alexander Graf 2010-12-08 12:05:45 +01:00 committed by Blue Swirl
parent 387c3e96bf
commit 0d2a73b3ab
1 changed files with 2 additions and 15 deletions
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17
hw/ppc4xx_pci.c
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@ -24,7 +24,6 @@
#include "ppc4xx.h" #include "ppc4xx.h"
#include "pci.h" #include "pci.h"
#include "pci_host.h" #include "pci_host.h"
#include "bswap.h"
#undef DEBUG #undef DEBUG
#ifdef DEBUG #ifdef DEBUG
@ -102,10 +101,6 @@ static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
{ {
PPC4xxPCIState *ppc4xx_pci = opaque; PPC4xxPCIState *ppc4xx_pci = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
ppc4xx_pci->pci_state.config_reg = value & ~0x3; ppc4xx_pci->pci_state.config_reg = value & ~0x3;
} }
@ -120,10 +115,6 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
{ {
struct PPC4xxPCIState *pci = opaque; struct PPC4xxPCIState *pci = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
/* We ignore all target attempts at PCI configuration, effectively /* We ignore all target attempts at PCI configuration, effectively
* assuming a bidirectional 1:1 mapping of PLB and PCI space. */ * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
@ -251,10 +242,6 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
value = 0; value = 0;
} }
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
return value; return value;
} }
@ -373,7 +360,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
/* CFGADDR */ /* CFGADDR */
index = cpu_register_io_memory(pci4xx_cfgaddr_read, index = cpu_register_io_memory(pci4xx_cfgaddr_read,
pci4xx_cfgaddr_write, controller, pci4xx_cfgaddr_write, controller,
DEVICE_NATIVE_ENDIAN); DEVICE_LITTLE_ENDIAN);
if (index < 0) if (index < 0)
goto free; goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
@ -386,7 +373,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
/* Internal registers */ /* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
DEVICE_NATIVE_ENDIAN); DEVICE_LITTLE_ENDIAN);
if (index < 0) if (index < 0)
goto free; goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index); cpu_register_physical_memory(registers, PCI_REG_SIZE, index);