target/ppc/mmu_common.c: Inline and remove ppc6xx_tlb_pte_check()
This function is only called once and we can make the caller simpler by inlining it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -91,33 +91,6 @@ int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
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return nr;
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}
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static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int pteh,
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MMUAccessType access_type, bool nx)
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{
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/* Check validity and table match */
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if (!pte_is_valid(pte0) || ((pte0 >> 6) & 1) != pteh ||
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(pte0 & PTE_PTEM_MASK) != ctx->ptem) {
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return -1;
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}
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/* all matches should have equal RPN, WIMG & PP */
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if (ctx->raddr != (hwaddr)-1ULL &&
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(ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
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qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n");
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return -3;
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}
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/* Keep the matching PTE information */
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ctx->raddr = pte1;
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ctx->prot = ppc_hash32_prot(ctx->key, pte1 & HPTE32_R_PP, nx);
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if (check_prot_access_type(ctx->prot, access_type)) {
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qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
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return 0;
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} else {
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qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
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return -2;
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}
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}
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/* Software driven TLB helpers */
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static int ppc6xx_tlb_check(CPUPPCState *env,
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@ -149,32 +122,32 @@ static int ppc6xx_tlb_check(CPUPPCState *env,
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tlb->EPN, eaddr, tlb->pte1,
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access_type == MMU_DATA_STORE ? 'S' : 'L',
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access_type == MMU_INST_FETCH ? 'I' : 'D');
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1,
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0, access_type, nx)) {
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case -2:
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/* Access violation */
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ret = -2;
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best = nr;
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break;
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case -1: /* No match */
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case -3: /* TLB inconsistency */
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default:
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break;
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case 0:
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/* access granted */
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/*
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* XXX: we should go on looping to check all TLBs
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* consistency but we can speed-up the whole thing as
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* the result would be undefined if TLBs are not
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* consistent.
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*/
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/* Check validity and table match */
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if (!pte_is_valid(tlb->pte0) || ((tlb->pte0 >> 6) & 1) != 0 ||
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(tlb->pte0 & PTE_PTEM_MASK) != ctx->ptem) {
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continue;
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}
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/* all matches should have equal RPN, WIMG & PP */
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if (ctx->raddr != (hwaddr)-1ULL &&
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(ctx->raddr & PTE_CHECK_MASK) != (tlb->pte1 & PTE_CHECK_MASK)) {
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qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n");
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/* TLB inconsistency */
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continue;
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}
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/* Keep the matching PTE information */
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best = nr;
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ctx->raddr = tlb->pte1;
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ctx->prot = ppc_hash32_prot(ctx->key, tlb->pte1 & HPTE32_R_PP, nx);
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if (check_prot_access_type(ctx->prot, access_type)) {
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qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
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ret = 0;
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best = nr;
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goto done;
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break;
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} else {
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qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
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ret = -2;
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}
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}
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if (best != -1) {
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done:
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qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx
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" prot=%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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