ppc_prep: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
parent
c92bb2c725
commit
0c90c52fab
107
hw/ppc_prep.c
107
hw/ppc_prep.c
@ -116,16 +116,17 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
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/* PCI intack register */
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/* Read-only register (?) */
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static void _PPC_intack_write (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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#if 0
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
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value);
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#endif
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}
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static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
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static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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uint32_t retval = 0;
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@ -139,31 +140,10 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
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return retval;
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}
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
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{
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return _PPC_intack_read(addr);
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}
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
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{
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return _PPC_intack_read(addr);
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}
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
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{
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return _PPC_intack_read(addr);
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}
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static CPUWriteMemoryFunc * const PPC_intack_write[] = {
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&_PPC_intack_write,
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&_PPC_intack_write,
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&_PPC_intack_write,
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};
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static CPUReadMemoryFunc * const PPC_intack_read[] = {
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&PPC_intack_readb,
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&PPC_intack_readw,
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&PPC_intack_readl,
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static const MemoryRegionOps PPC_intack_ops = {
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.read = PPC_intack_read,
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.write = PPC_intack_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* PowerPC control and status registers */
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@ -244,17 +224,14 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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return retval;
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}
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static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
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&PPC_XCSR_writeb,
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&PPC_XCSR_writew,
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&PPC_XCSR_writel,
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static const MemoryRegionOps PPC_XCSR_ops = {
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.old_mmio = {
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.read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
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.write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
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&PPC_XCSR_readb,
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&PPC_XCSR_readw,
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&PPC_XCSR_readl,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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@ -503,16 +480,12 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
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return ret;
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}
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static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
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&PPC_prep_io_writeb,
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&PPC_prep_io_writew,
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&PPC_prep_io_writel,
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};
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static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
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&PPC_prep_io_readb,
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&PPC_prep_io_readw,
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&PPC_prep_io_readl,
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static const MemoryRegionOps PPC_prep_io_ops = {
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.old_mmio = {
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.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
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.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define NVRAM_SIZE 0x2000
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@ -534,13 +507,19 @@ static void ppc_prep_init (ram_addr_t ram_size,
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const char *initrd_filename,
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const char *cpu_model)
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{
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MemoryRegion *sysmem = get_system_memory();
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CPUState *env = NULL;
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char *filename;
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nvram_t nvram;
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M48t59State *m48t59;
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int PPC_io_memory;
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MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
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MemoryRegion *intack = g_new(MemoryRegion, 1);
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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int linux_boot, i, nb_nics1, bios_size;
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ram_addr_t ram_offset, bios_offset;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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uint32_t kernel_base, initrd_base;
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long kernel_size, initrd_size;
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PCIBus *pci_bus;
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@ -574,11 +553,11 @@ static void ppc_prep_init (ram_addr_t ram_size,
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}
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/* allocate RAM */
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ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size);
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cpu_register_physical_memory(0, ram_size, ram_offset);
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memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
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memory_region_add_subregion(sysmem, 0, ram);
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/* allocate and load BIOS */
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bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE);
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memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE);
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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@ -591,8 +570,8 @@ static void ppc_prep_init (ram_addr_t ram_size,
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target_phys_addr_t bios_addr;
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bios_size = (bios_size + 0xfff) & ~0xfff;
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bios_addr = (uint32_t)(-bios_size);
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cpu_register_physical_memory(bios_addr, bios_size,
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bios_offset | IO_MEM_ROM);
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(sysmem, bios_addr, bios);
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bios_size = load_image_targphys(filename, bios_addr, bios_size);
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}
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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@ -655,10 +634,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
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isa_bus_irqs(i8259);
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// pci_bus = i440fx_init();
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/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
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PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
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PPC_prep_io_write, sysctrl,
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DEVICE_LITTLE_ENDIAN);
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cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
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memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
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"ppc-io", 0x00800000);
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memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
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/* init basic PC hardware */
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pci_vga_init(pci_bus);
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@ -713,15 +691,12 @@ static void ppc_prep_init (ram_addr_t ram_size,
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register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
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register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
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/* PCI intack location */
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PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
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PPC_intack_write, NULL,
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DEVICE_LITTLE_ENDIAN);
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cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
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memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4);
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memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack);
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/* PowerPC control and status register group */
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#if 0
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PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
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NULL, DEVICE_LITTLE_ENDIAN);
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cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
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memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
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memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
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#endif
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if (usb_enabled) {
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