hw/intc: Add (new) ASPEED VIC device model
Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with enough functionality to boot an aspeed_defconfig Linux kernel. The model implements the 'new' (revised) register set: While the hardware exposes both the new and legacy register sets, accesses to the model's legacy register set will not be serviced (however the access will be logged). [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Jeffery
Peter Maydell
parent
c04bd47db6
commit
0c69996e22
@ -31,3 +31,4 @@ obj-$(CONFIG_XICS_KVM) += xics_kvm.o
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obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
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obj-$(CONFIG_S390_FLIC) += s390_flic.o
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obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o
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obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o
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339
hw/intc/aspeed_vic.c
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339
hw/intc/aspeed_vic.c
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@ -0,0 +1,339 @@
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/*
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* ASPEED Interrupt Controller (New)
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2015, 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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/* The hardware exposes two register sets, a legacy set and a 'new' set. The
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* model implements the 'new' register set, and logs warnings on accesses to
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* the legacy IO space.
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*
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* The hardware uses 32bit registers to manage 51 IRQs, with low and high
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* registers for each conceptual register. The device model's implementation
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* uses 64bit data types to store both low and high register values (in the one
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* member), but must cope with access offset values in multiples of 4 passed to
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* the callbacks. As such the read() and write() implementations process the
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* provided offset to understand whether the access is requesting the lower or
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* upper 32 bits of the 64bit member.
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*
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* Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
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* fields have separate "enable"/"status" and "clear" registers, where set bits
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* are written to one or the other to change state (avoiding a
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* read-modify-write sequence).
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*/
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#include "qemu/osdep.h"
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#include <inttypes.h>
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#include "hw/intc/aspeed_vic.h"
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#include "qemu/bitops.h"
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#include "trace.h"
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#define AVIC_NEW_BASE_OFFSET 0x80
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#define AVIC_L_MASK 0xFFFFFFFFU
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#define AVIC_H_MASK 0x0007FFFFU
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#define AVIC_EVENT_W_MASK (0x78000ULL << 32)
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static void aspeed_vic_update(AspeedVICState *s)
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{
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uint64_t new = (s->raw & s->enable);
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uint64_t flags;
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flags = new & s->select;
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trace_aspeed_vic_update_fiq(!!flags);
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qemu_set_irq(s->fiq, !!flags);
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flags = new & ~s->select;
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trace_aspeed_vic_update_irq(!!flags);
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qemu_set_irq(s->irq, !!flags);
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}
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static void aspeed_vic_set_irq(void *opaque, int irq, int level)
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{
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uint64_t irq_mask;
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bool raise;
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AspeedVICState *s = (AspeedVICState *)opaque;
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if (irq > ASPEED_VIC_NR_IRQS) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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__func__, irq);
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return;
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}
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trace_aspeed_vic_set_irq(irq, level);
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irq_mask = BIT(irq);
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if (s->sense & irq_mask) {
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/* level-triggered */
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if (s->event & irq_mask) {
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/* high-sensitive */
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raise = level;
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} else {
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/* low-sensitive */
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raise = !level;
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}
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s->raw = deposit64(s->raw, irq, 1, raise);
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} else {
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uint64_t old_level = s->level & irq_mask;
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/* edge-triggered */
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if (s->dual_edge & irq_mask) {
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raise = (!!old_level) != (!!level);
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} else {
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if (s->event & irq_mask) {
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/* rising-sensitive */
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raise = !old_level && level;
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} else {
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/* falling-sensitive */
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raise = old_level && !level;
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}
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}
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if (raise) {
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s->raw = deposit64(s->raw, irq, 1, raise);
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}
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}
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s->level = deposit64(s->level, irq, 1, level);
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aspeed_vic_update(s);
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}
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static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint64_t val;
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const bool high = !!(offset & 0x4);
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hwaddr n_offset = (offset & ~0x4);
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AspeedVICState *s = (AspeedVICState *)opaque;
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if (offset < AVIC_NEW_BASE_OFFSET) {
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qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
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"at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
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return 0;
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}
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n_offset -= AVIC_NEW_BASE_OFFSET;
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switch (n_offset) {
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case 0x0: /* IRQ Status */
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val = s->raw & ~s->select & s->enable;
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break;
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case 0x08: /* FIQ Status */
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val = s->raw & s->select & s->enable;
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break;
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case 0x10: /* Raw Interrupt Status */
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val = s->raw;
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break;
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case 0x18: /* Interrupt Selection */
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val = s->select;
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break;
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case 0x20: /* Interrupt Enable */
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val = s->enable;
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break;
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case 0x30: /* Software Interrupt */
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val = s->trigger;
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break;
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case 0x40: /* Interrupt Sensitivity */
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val = s->sense;
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break;
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case 0x48: /* Interrupt Both Edge Trigger Control */
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val = s->dual_edge;
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break;
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case 0x50: /* Interrupt Event */
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val = s->event;
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break;
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case 0x60: /* Edge Triggered Interrupt Status */
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val = s->raw & ~s->sense;
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break;
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/* Illegal */
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case 0x28: /* Interrupt Enable Clear */
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case 0x38: /* Software Interrupt Clear */
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case 0x58: /* Edge Triggered Interrupt Clear */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Read of write-only register with offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);
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val = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad register at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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val = 0;
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break;
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}
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if (high) {
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val = extract64(val, 32, 19);
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}
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trace_aspeed_vic_read(offset, size, val);
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return val;
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}
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static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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const bool high = !!(offset & 0x4);
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hwaddr n_offset = (offset & ~0x4);
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AspeedVICState *s = (AspeedVICState *)opaque;
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if (offset < AVIC_NEW_BASE_OFFSET) {
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qemu_log_mask(LOG_UNIMP,
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"%s: Ignoring write to legacy registers at 0x%"
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HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
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size, data);
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return;
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}
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n_offset -= AVIC_NEW_BASE_OFFSET;
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trace_aspeed_vic_write(offset, size, data);
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/* Given we have members using separate enable/clear registers, deposit64()
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* isn't quite the tool for the job. Instead, relocate the incoming bits to
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* the required bit offset based on the provided access address
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*/
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if (high) {
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data &= AVIC_H_MASK;
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data <<= 32;
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} else {
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data &= AVIC_L_MASK;
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}
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switch (n_offset) {
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case 0x18: /* Interrupt Selection */
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/* Register has deposit64() semantics - overwrite requested 32 bits */
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if (high) {
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s->select &= AVIC_L_MASK;
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} else {
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s->select &= ((uint64_t) AVIC_H_MASK) << 32;
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}
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s->select |= data;
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break;
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case 0x20: /* Interrupt Enable */
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s->enable |= data;
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break;
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case 0x28: /* Interrupt Enable Clear */
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s->enable &= ~data;
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break;
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case 0x30: /* Software Interrupt */
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qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
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"IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
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break;
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case 0x38: /* Software Interrupt Clear */
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qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
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"IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
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break;
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case 0x50: /* Interrupt Event */
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/* Register has deposit64() semantics - overwrite the top four valid
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* IRQ bits, as only the top four IRQs (GPIOs) can change their event
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* type */
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if (high) {
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s->event &= ~AVIC_EVENT_W_MASK;
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s->event |= (data & AVIC_EVENT_W_MASK);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Ignoring invalid write to interrupt event register");
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}
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break;
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case 0x58: /* Edge Triggered Interrupt Clear */
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s->raw &= ~(data & ~s->sense);
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break;
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case 0x00: /* IRQ Status */
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case 0x08: /* FIQ Status */
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case 0x10: /* Raw Interrupt Status */
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case 0x40: /* Interrupt Sensitivity */
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case 0x48: /* Interrupt Both Edge Trigger Control */
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case 0x60: /* Edge Triggered Interrupt Status */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write of read-only register with offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad register at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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aspeed_vic_update(s);
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}
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static const MemoryRegionOps aspeed_vic_ops = {
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.read = aspeed_vic_read,
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.write = aspeed_vic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void aspeed_vic_reset(DeviceState *dev)
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{
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AspeedVICState *s = ASPEED_VIC(dev);
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s->level = 0;
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s->raw = 0;
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s->select = 0;
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s->enable = 0;
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s->trigger = 0;
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s->sense = 0x1F07FFF8FFFFULL;
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s->dual_edge = 0xF800070000ULL;
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s->event = 0x5F07FFF8FFFFULL;
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}
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#define AVIC_IO_REGION_SIZE 0x20000
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static void aspeed_vic_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedVICState *s = ASPEED_VIC(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_vic_ops, s,
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TYPE_ASPEED_VIC, AVIC_IO_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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qdev_init_gpio_in(dev, aspeed_vic_set_irq, ASPEED_VIC_NR_IRQS);
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sysbus_init_irq(sbd, &s->irq);
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sysbus_init_irq(sbd, &s->fiq);
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}
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static const VMStateDescription vmstate_aspeed_vic = {
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.name = "aspeed.new-vic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(level, AspeedVICState),
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VMSTATE_UINT64(raw, AspeedVICState),
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VMSTATE_UINT64(select, AspeedVICState),
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VMSTATE_UINT64(enable, AspeedVICState),
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VMSTATE_UINT64(trigger, AspeedVICState),
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VMSTATE_UINT64(sense, AspeedVICState),
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VMSTATE_UINT64(dual_edge, AspeedVICState),
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VMSTATE_UINT64(event, AspeedVICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void aspeed_vic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_vic_realize;
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dc->reset = aspeed_vic_reset;
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dc->desc = "ASPEED Interrupt Controller (New)";
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dc->vmsd = &vmstate_aspeed_vic;
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}
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static const TypeInfo aspeed_vic_info = {
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.name = TYPE_ASPEED_VIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedVICState),
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.class_init = aspeed_vic_class_init,
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};
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static void aspeed_vic_register_types(void)
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{
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type_register_static(&aspeed_vic_info);
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}
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type_init(aspeed_vic_register_types);
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48
include/hw/intc/aspeed_vic.h
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48
include/hw/intc/aspeed_vic.h
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@ -0,0 +1,48 @@
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/*
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* ASPEED Interrupt Controller (New)
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* Need to add SVIC and CVIC support
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*/
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#ifndef ASPEED_VIC_H
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#define ASPEED_VIC_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_VIC "aspeed.vic"
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#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
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#define ASPEED_VIC_NR_IRQS 51
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typedef struct AspeedVICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq fiq;
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uint64_t level;
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uint64_t raw;
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uint64_t select;
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uint64_t enable;
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uint64_t trigger;
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/* 0=edge, 1=level */
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uint64_t sense;
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/* 0=single-edge, 1=dual-edge */
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uint64_t dual_edge;
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/* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
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uint64_t event;
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} AspeedVICState;
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#endif /* ASPEED_VIC_H */
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@ -1901,3 +1901,10 @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
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aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
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aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
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aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
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# hw/intc/aspeed_vic.c
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aspeed_vic_set_irq(int irq, int level) "Enabling IRQ %d: %d"
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aspeed_vic_update_fiq(int flags) "Raising FIQ: %d"
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aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
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aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
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aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
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