Fixes for rc4:
* Fix compile failures of C++ files with new glib headers * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU * accel/tcg: Fix assertion failure executing from non-RAM with -icount -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmB7OY4ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tG9EACDzCnu0pfeizTDmemgdoxR aWYcr/vl0sPpA1wXlGFurtRX1dTeVcX+aA0qH752jLXzfNYYR7X1QDCqOn4XTMJk hACCyDBc1J0lHCrvgAEkx6A8yoSn2yaT27uoMvgeU5qX88/wOBIeZbH5Gti/BrIr hg5yg0IiQnCqFu897WPo4+F8sjvOaJEcPy7E0LhUzES6IiKWGfonKQh+QNI/1hsz Q4wtSSQSsACrnWIL9kcmjtNjrO0nY4tk3v7hgeLJq7bMZ2yOQ/h6A570o//AfUti pr1XaviCtpJDjeP3/gmyEPtIhjGzPX1GDdaX9+Ptr0qmwDj7Ygzel9NJrQklWvHY EDN5JeGp9yrashCYrgQHNO236f3+8OvXhVSNEcnlViV8naSaw4XL8vAAQN6Qp8tB BVuV+r+i5DQxl3O2ILu5mLdhi65sAzaRdHGPhQXeUb0OWviWDBX7G4scnWik2qSy LwUWSAtU+G7/4nY+AvA1d2Q+/viTZ4IgpAm/AvAlcUevCOGcF2LT7hCnk1isdX2S nZ0UPmi3DbUG358ipi8nZKvgRCTHofsMJXxmx3p+WPy9AEnKep9SEYFeH33bfnNP cSlBRn9JjHvr7vO0cOmRAmvjQMK4ioxCl7LlDR1/KPEwWFzdZAD1Yx3JhqXaxpcw g+PADYJHQej3JDpHyRtsZA== =/6nB -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210417' into staging Fixes for rc4: * Fix compile failures of C++ files with new glib headers * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU * accel/tcg: Fix assertion failure executing from non-RAM with -icount # gpg: Signature made Sat 17 Apr 2021 20:39:58 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210417: accel/tcg: avoid re-translating one-shot instructions target/arm: drop CF_LAST_IO/dc->condjump check hw/arm/armsse: Make SSE-300 use Cortex-M55 hw/arm/armsse: Give SSE-300 its own Property array include/qemu/osdep.h: Move system includes to top osdep: protect qemu/osdep.h with extern "C" osdep: include glib-compat.h before other QEMU headers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
0c5393a134
@ -1863,7 +1863,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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if (phys_pc == -1) {
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/* Generate a one-shot TB with 1 insn in it */
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cflags = (cflags & ~CF_COUNT_MASK) | 1;
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cflags = (cflags & ~CF_COUNT_MASK) | CF_LAST_IO | 1;
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}
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max_insns = cflags & CF_COUNT_MASK;
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@ -17,8 +17,8 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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extern "C" {
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#include "qemu/osdep.h"
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extern "C" {
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#include "disas/dis-asm.h"
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}
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@ -27,8 +27,8 @@
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* Reference Manual", Revision 01.01, April 27, 2018
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*/
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extern "C" {
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#include "qemu/osdep.h"
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extern "C" {
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#include "disas/dis-asm.h"
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}
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@ -56,6 +56,7 @@ typedef struct ARMSSEDeviceInfo {
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struct ARMSSEInfo {
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const char *name;
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const char *cpu_type;
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uint32_t sse_version;
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int sram_banks;
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int num_cpus;
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@ -84,7 +85,7 @@ static Property iotkit_properties[] = {
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DEFINE_PROP_END_OF_LIST()
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};
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static Property armsse_properties[] = {
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static Property sse200_properties[] = {
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DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
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@ -97,6 +98,17 @@ static Property armsse_properties[] = {
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DEFINE_PROP_END_OF_LIST()
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};
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static Property sse300_properties[] = {
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DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
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DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
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DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
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DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
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DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
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DEFINE_PROP_END_OF_LIST()
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};
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static const ARMSSEDeviceInfo iotkit_devices[] = {
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{
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.name = "timer0",
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@ -490,6 +502,7 @@ static const ARMSSEInfo armsse_variants[] = {
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{
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.name = TYPE_IOTKIT,
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.sse_version = ARMSSE_IOTKIT,
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.cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
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.sram_banks = 1,
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.num_cpus = 1,
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.sys_version = 0x41743,
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@ -508,6 +521,7 @@ static const ARMSSEInfo armsse_variants[] = {
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{
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.name = TYPE_SSE200,
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.sse_version = ARMSSE_SSE200,
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.cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
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.sram_banks = 4,
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.num_cpus = 2,
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.sys_version = 0x22041743,
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@ -519,13 +533,14 @@ static const ARMSSEInfo armsse_variants[] = {
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.has_cpuid = true,
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.has_cpu_pwrctrl = false,
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.has_sse_counter = false,
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.props = armsse_properties,
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.props = sse200_properties,
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.devinfo = sse200_devices,
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.irq_is_common = sse200_irq_is_common,
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},
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{
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.name = TYPE_SSE300,
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.sse_version = ARMSSE_SSE300,
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.cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"),
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.sram_banks = 2,
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.num_cpus = 1,
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.sys_version = 0x7e00043b,
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@ -537,7 +552,7 @@ static const ARMSSEInfo armsse_variants[] = {
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.has_cpuid = true,
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.has_cpu_pwrctrl = true,
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.has_sse_counter = true,
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.props = armsse_properties,
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.props = sse300_properties,
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.devinfo = sse300_devices,
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.irq_is_common = sse300_irq_is_common,
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},
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@ -708,8 +723,7 @@ static void armsse_init(Object *obj)
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name = g_strdup_printf("armv7m%d", i);
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object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
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TYPE_ARMV7M);
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qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type",
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ARM_CPU_TYPE_NAME("cortex-m33"));
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qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type);
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g_free(name);
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name = g_strdup_printf("arm-sse-cpu-container%d", i);
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memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX);
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@ -11,6 +11,12 @@
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#define QEMU_STATIC_ANALYSIS 1
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#endif
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#ifdef __cplusplus
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#define QEMU_EXTERN_C extern "C"
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#else
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#define QEMU_EXTERN_C extern
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#endif
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#define QEMU_NORETURN __attribute__ ((__noreturn__))
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#define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
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@ -57,7 +57,7 @@
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#define daemon qemu_fake_daemon_function
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#include <stdlib.h>
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#undef daemon
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extern int daemon(int, int);
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QEMU_EXTERN_C int daemon(int, int);
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#endif
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#ifdef _WIN32
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@ -104,6 +104,15 @@ extern int daemon(int, int);
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#include <setjmp.h>
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#include <signal.h>
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#ifdef CONFIG_IOVEC
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#include <sys/uio.h>
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#endif
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#if defined(__linux__) && defined(__sparc__)
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/* The SPARC definition of QEMU_VMALLOC_ALIGN needs SHMLBA */
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#include <sys/shm.h>
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#endif
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#ifndef _WIN32
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#include <sys/wait.h>
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#else
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@ -111,6 +120,21 @@ extern int daemon(int, int);
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#define WEXITSTATUS(x) (x)
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#endif
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#ifdef __APPLE__
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#include <AvailabilityMacros.h>
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#endif
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/*
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* This is somewhat like a system header; it must be outside any extern "C"
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* block because it includes system headers itself, including glib.h,
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* which will not compile if inside an extern "C" block.
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*/
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#include "glib-compat.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _WIN32
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#include "sysemu/os-win32.h"
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#endif
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@ -119,11 +143,6 @@ extern int daemon(int, int);
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#include "sysemu/os-posix.h"
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#endif
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#ifdef __APPLE__
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#include <AvailabilityMacros.h>
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#endif
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#include "glib-compat.h"
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#include "qemu/typedefs.h"
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/*
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@ -459,7 +478,6 @@ void qemu_anon_ram_free(void *ptr, size_t size);
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/* Use 1 MiB (segment size) alignment so gmap can be used by KVM. */
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# define QEMU_VMALLOC_ALIGN (256 * 4096)
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#elif defined(__linux__) && defined(__sparc__)
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#include <sys/shm.h>
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# define QEMU_VMALLOC_ALIGN MAX(qemu_real_host_page_size, SHMLBA)
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#else
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# define QEMU_VMALLOC_ALIGN qemu_real_host_page_size
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@ -539,8 +557,6 @@ struct iovec {
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ssize_t readv(int fd, const struct iovec *iov, int iov_cnt);
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ssize_t writev(int fd, const struct iovec *iov, int iov_cnt);
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#else
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#include <sys/uio.h>
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#endif
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#ifdef _WIN32
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@ -722,4 +738,8 @@ static inline int platform_does_not_support_system(const char *command)
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}
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#endif /* !HAVE_SYSTEM_FUNCTION */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -9199,11 +9199,6 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (tb_cflags(dc->base.tb) & CF_LAST_IO && dc->condjmp) {
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/* FIXME: This can theoretically happen with self-modifying code. */
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cpu_abort(cpu, "IO on conditional branch instruction");
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}
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/* At this stage dc->condjmp will only be set when the skipped
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instruction was a conditional branch or trap, and the PC has
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already been written. */
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