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target/riscv: Define macros and variables for ss1p13

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Add macros and variables for RISC-V privilege 1.13 support.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-3-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Fea.Wang 2024-06-06 21:54:50 +08:00 committed by Alistair Francis
parent a1a8e7768f
commit 0c2d5f7396
2 changed files with 4 additions and 1 deletions
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4
target/riscv/cpu.h
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@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
#define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_10_0_STR "v1.10.0"
#define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_11_0_STR "v1.11.0"
#define PRIV_VER_1_12_0_STR "v1.12.0" #define PRIV_VER_1_12_0_STR "v1.12.0"
#define PRIV_VER_1_13_0_STR "v1.13.0"
enum { enum {
PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0, PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0, PRIV_VERSION_1_12_0,
PRIV_VERSION_1_13_0,
PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
}; };
#define VEXT_VERSION_1_00_0 0x00010000 #define VEXT_VERSION_1_00_0 0x00010000

1
target/riscv/cpu_cfg.h
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@ -136,6 +136,7 @@ struct RISCVCPUConfig {
* TCG always implement/can't be user disabled, * TCG always implement/can't be user disabled,
* based on spec version. * based on spec version.
*/ */
bool has_priv_1_13;
bool has_priv_1_12; bool has_priv_1_12;
bool has_priv_1_11; bool has_priv_1_11;