linux-user: Determine the desired FPU mode from MIPS.abiflags
Floating-point mode is calculated from MIPS.abiflags FP ABI value (based on kernel implementation). Illegal combinations are rejected. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -740,6 +740,34 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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struct image_info *info = ts->info;
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int i;
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struct mode_req {
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bool single;
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bool soft;
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bool fr1;
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bool frdefault;
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bool fre;
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};
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static const struct mode_req fpu_reqs[] = {
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[MIPS_ABI_FP_ANY] = { true, true, true, true, true },
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[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
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[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
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[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
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[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
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[MIPS_ABI_FP_XX] = { false, false, true, true, true },
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[MIPS_ABI_FP_64] = { false, false, true, false, false },
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[MIPS_ABI_FP_64A] = { false, false, true, false, true }
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};
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/*
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* Mode requirements when .MIPS.abiflags is not present in the ELF.
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* Not present means that everything is acceptable except FR1.
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*/
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static struct mode_req none_req = { true, true, false, true, true };
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struct mode_req prog_req;
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struct mode_req interp_req;
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for(i = 0; i < 32; i++) {
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env->active_tc.gpr[i] = regs->regs[i];
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}
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@ -747,6 +775,53 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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if (regs->cp0_epc & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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}
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#ifdef TARGET_ABI_MIPSO32
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# define MAX_FP_ABI MIPS_ABI_FP_64A
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#else
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# define MAX_FP_ABI MIPS_ABI_FP_SOFT
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#endif
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if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
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|| (info->interp_fp_abi > MAX_FP_ABI &&
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info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
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fprintf(stderr, "qemu: Unexpected FPU mode\n");
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exit(1);
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}
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prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
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: fpu_reqs[info->fp_abi];
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interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
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: fpu_reqs[info->interp_fp_abi];
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prog_req.single &= interp_req.single;
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prog_req.soft &= interp_req.soft;
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prog_req.fr1 &= interp_req.fr1;
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prog_req.frdefault &= interp_req.frdefault;
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prog_req.fre &= interp_req.fre;
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bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
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env->insn_flags & ISA_MIPS64R2 ||
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env->insn_flags & ISA_MIPS32R6 ||
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env->insn_flags & ISA_MIPS64R6;
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if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
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env->CP0_Config5 |= (1 << CP0C5_FRE);
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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} else if ((prog_req.fr1 && prog_req.frdefault) ||
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(prog_req.single && !prog_req.frdefault)) {
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if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
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&& cpu_has_mips_r2_r6) || prog_req.fr1) {
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env->CP0_Status |= (1 << CP0St_FR);
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env->hflags |= MIPS_HFLAG_F64;
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}
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} else if (!prog_req.fre && !prog_req.frdefault &&
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!prog_req.fr1 && !prog_req.single && !prog_req.soft) {
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fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
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exit(1);
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}
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if (env->insn_flags & ISA_NANOMIPS32) {
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return;
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}
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