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target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

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Introduce the PEXTUW opcode (Parallel Extend Upper from Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-12-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 20:42:14 +01:00
parent 709324dc05
commit 0bc6937296
2 changed files with 34 additions and 0 deletions
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4
target/mips/tcg/tx79.decode
View File

@ -35,6 +35,10 @@ PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
# MMI1
PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd

30
target/mips/tcg/tx79_translate.c
View File

@ -290,6 +290,36 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
* PEXTLW rd, rs, rt Parallel Extend Lower from Word
*/
static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_deposit_i64(dl, b, a, 32, 32);
tcg_gen_shri_i64(b, b, 32);
tcg_gen_deposit_i64(dh, a, b, 0, 32);
}
/* Parallel Extend Upper from Word */
static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
{
TCGv_i64 ax, bx;
if (a->rd == 0) {
/* nop */
return true;
}
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
/*
* Others (16 instructions)
* ------------------------