target-i386: add feature flags for CPUID[EAX=0xd,ECX=1]
These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -274,6 +274,17 @@ static const char *cpuid_apm_edx_feature_name[] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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};
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};
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static const char *cpuid_xsave_feature_name[] = {
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"xsaveopt", "xsavec", "xgetbv1", "xsaves",
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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};
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
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@ -391,6 +402,14 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.tcg_features = TCG_APM_FEATURES,
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.tcg_features = TCG_APM_FEATURES,
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.unmigratable_flags = CPUID_APM_INVTSC,
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.unmigratable_flags = CPUID_APM_INVTSC,
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},
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},
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[FEAT_XSAVE] = {
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.feat_names = cpuid_xsave_feature_name,
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.cpuid_eax = 0xd,
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.cpuid_needs_ecx = true, .cpuid_ecx = 1,
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.cpuid_reg = R_EAX,
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.tcg_features = 0,
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.unmigratable_flags = FEAT_XSAVES,
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},
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};
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};
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typedef struct X86RegisterInfo32 {
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typedef struct X86RegisterInfo32 {
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@ -1018,6 +1037,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_SYSCALL,
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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CPUID_EXT3_LAHF_LM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.xlevel = 0x8000000A,
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.xlevel = 0x8000000A,
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.model_id = "Intel Xeon E312xx (Sandy Bridge)",
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.model_id = "Intel Xeon E312xx (Sandy Bridge)",
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},
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},
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@ -1051,6 +1072,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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CPUID_7_0_EBX_RTM,
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CPUID_7_0_EBX_RTM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.xlevel = 0x8000000A,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Haswell)",
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.model_id = "Intel Core Processor (Haswell)",
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},
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},
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@ -1085,6 +1108,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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CPUID_7_0_EBX_SMAP,
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CPUID_7_0_EBX_SMAP,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.xlevel = 0x8000000A,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Broadwell)",
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.model_id = "Intel Core Processor (Broadwell)",
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},
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},
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@ -1202,6 +1227,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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CPUID_EXT3_LAHF_LM,
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CPUID_EXT3_LAHF_LM,
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/* no xsaveopt! */
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.xlevel = 0x8000001A,
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.xlevel = 0x8000001A,
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.model_id = "AMD Opteron 62xx class CPU",
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.model_id = "AMD Opteron 62xx class CPU",
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},
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},
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@ -1236,6 +1262,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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CPUID_EXT3_LAHF_LM,
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CPUID_EXT3_LAHF_LM,
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/* no xsaveopt! */
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.xlevel = 0x8000001A,
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.xlevel = 0x8000001A,
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.model_id = "AMD Opteron 63xx class CPU",
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.model_id = "AMD Opteron 63xx class CPU",
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},
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},
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@ -2377,7 +2404,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
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*eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
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*ebx = *ecx;
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*ebx = *ecx;
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} else if (count == 1) {
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} else if (count == 1) {
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*eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
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*eax = env->features[FEAT_XSAVE];
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} else if (count < ARRAY_SIZE(ext_save_areas)) {
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} else if (count < ARRAY_SIZE(ext_save_areas)) {
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const ExtSaveArea *esa = &ext_save_areas[count];
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const ExtSaveArea *esa = &ext_save_areas[count];
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if ((env->features[esa->feature] & esa->bits) == esa->bits &&
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if ((env->features[esa->feature] & esa->bits) == esa->bits &&
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@ -411,6 +411,7 @@ typedef enum FeatureWord {
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FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_SVM, /* CPUID[8000_000A].EDX */
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FEAT_SVM, /* CPUID[8000_000A].EDX */
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FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
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FEATURE_WORDS,
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FEATURE_WORDS,
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} FeatureWord;
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} FeatureWord;
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@ -571,6 +572,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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#define CPUID_XSAVE_XGETBV1 (1U << 2)
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#define CPUID_XSAVE_XSAVES (1U << 3)
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/* CPUID[0x80000007].EDX flags: */
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/* CPUID[0x80000007].EDX flags: */
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#define CPUID_APM_INVTSC (1U << 8)
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#define CPUID_APM_INVTSC (1U << 8)
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