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Misc HW patch queue

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Fixes for hardware used by machines running AmigaOS.
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Merge tag 'hw-misc-20240415' of https://github.com/philmd/qemu into staging

Misc HW patch queue

Fixes for hardware used by machines running AmigaOS.

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# gpg: Signature made Mon 15 Apr 2024 15:54:06 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20240415' of https://github.com/philmd/qemu:
  hw/pci-host/ppc440_pcix: Do not expose a bridge device on PCI bus
  hw/isa/vt82c686: Keep track of PIRQ/PINT pins separately

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-04-15 15:57:34 +01:00
commit 0b96f75b71
2 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/isa/vt82c686.c
View File

@ -658,7 +658,7 @@ void via_isa_set_irq(PCIDevice *d, int pin, int level)
ViaISAState *s = VIA_ISA(pci_get_function_0(d));
uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15;
int f = PCI_FUNC(d->devfn);
uint16_t mask = BIT(f);
uint16_t mask;
switch (f) {
case 0: /* PIRQ/PINT inputs */
@ -673,6 +673,7 @@ void via_isa_set_irq(PCIDevice *d, int pin, int level)
}
/* Keep track of the state of all sources */
mask = BIT(f);
if (level) {
s->irq_state[0] |= mask;
} else {

11
hw/pci-host/ppc440_pcix.c
View File

@ -52,7 +52,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPC440PCIXState, PPC440_PCIX_HOST)
struct PPC440PCIXState {
PCIHostState parent_obj;
PCIDevice *dev;
uint8_t config[PCI_CONFIG_SPACE_SIZE];
struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
uint32_t sts;
@ -171,7 +171,7 @@ static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
trace_ppc440_pcix_reg_write(addr, val, size);
switch (addr) {
case PCI_VENDOR_ID ... PCI_MAX_LAT:
stl_le_p(s->dev->config + addr, val);
stl_le_p(s->config + addr, val);
break;
case PCIX0_POM0LAL:
@ -302,7 +302,7 @@ static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
switch (addr) {
case PCI_VENDOR_ID ... PCI_MAX_LAT:
val = ldl_le_p(s->dev->config + addr);
val = ldl_le_p(s->config + addr);
break;
case PCIX0_POM0LAL:
@ -498,10 +498,7 @@ static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
memory_region_init(&s->iomem, OBJECT(dev), "pci-io", 64 * KiB);
h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq,
ppc440_pcix_map_irq, &s->irq, &s->busmem, &s->iomem,
PCI_DEVFN(0, 0), 1, TYPE_PCI_BUS);
s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0),
TYPE_PPC4xx_HOST_BRIDGE);
PCI_DEVFN(1, 0), 1, TYPE_PCI_BUS);
memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
memory_region_add_subregion(&s->bm, 0x0, &s->busmem);