target-arm queue:
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot * hw/intc: add implementation of GICD_IIDR to Arm GIC * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout * target/arm: Limit LPA2 effective output address when TCR.DS == 0 -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmN7disZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3i8sEACcJmCKplkJ3KlBqBCXdldF pNQde6fIAEvUtFGkPr8OLFixIp13aLlw3/7sieHl6o76GMw1u26kd/qTykypID/T j3rxZC7ospo2j3MfLLy0TiG/fwzCwa6G0SIdKUOjkwX52IgWE/gUlvtjJvtLcNEN nta2dm5PWcF6fxDZwdYUGo3akwi8qbIlBxUeQR3VTUzXC+7F22pDzA8lp8QpHeW0 inaLNtlEbRc5+rnOuwhOK5mnYiTwTN40vEz89v940Ii/CIFmPOAmx2rxsrmnVbLq uGqzXoN4OMurl2gco7LUMS2mshVBfpVOyZqaaXn/3dXkQ/W1fN37iCZF8Z2E8P2M YvcdxgYWoFmP7mlr9S1k4RgQTGVRS9j6XviGi62Zra2enNx5769JUhJFifQBYqLA V3FcizuHqUKsItJtGMO3gXR02BEE53o8c6WJ18uflTNVaY9wZ5MDqgGw/hKmfWLS /mjFdwwTbW7IZ0beW3pl9szXAduhGNoegTsfkn9xrANa62Jx1GSs/G0+mdSnA9oL 1YB2EDidiTlizbrn0aK+Lgls5/FG9qP+ReY7GhW2ZYvPuKesja6BJEAyEW6Xg3Sj D70L8/AzZtn8AHu/aKotLZ6UHVTNxFg4AHwte9fJYrZe72e6aR+8XQaCBPz47pi8 NHAnGWWc28SdNCau7I8uMg== =0yEm -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/sd: Fix sun4i allwinner-sdhost for U-Boot * hw/intc: add implementation of GICD_IIDR to Arm GIC * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout * target/arm: Limit LPA2 effective output address when TCR.DS == 0 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmN7disZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3i8sEACcJmCKplkJ3KlBqBCXdldF # pNQde6fIAEvUtFGkPr8OLFixIp13aLlw3/7sieHl6o76GMw1u26kd/qTykypID/T # j3rxZC7ospo2j3MfLLy0TiG/fwzCwa6G0SIdKUOjkwX52IgWE/gUlvtjJvtLcNEN # nta2dm5PWcF6fxDZwdYUGo3akwi8qbIlBxUeQR3VTUzXC+7F22pDzA8lp8QpHeW0 # inaLNtlEbRc5+rnOuwhOK5mnYiTwTN40vEz89v940Ii/CIFmPOAmx2rxsrmnVbLq # uGqzXoN4OMurl2gco7LUMS2mshVBfpVOyZqaaXn/3dXkQ/W1fN37iCZF8Z2E8P2M # YvcdxgYWoFmP7mlr9S1k4RgQTGVRS9j6XviGi62Zra2enNx5769JUhJFifQBYqLA # V3FcizuHqUKsItJtGMO3gXR02BEE53o8c6WJ18uflTNVaY9wZ5MDqgGw/hKmfWLS # /mjFdwwTbW7IZ0beW3pl9szXAduhGNoegTsfkn9xrANa62Jx1GSs/G0+mdSnA9oL # 1YB2EDidiTlizbrn0aK+Lgls5/FG9qP+ReY7GhW2ZYvPuKesja6BJEAyEW6Xg3Sj # D70L8/AzZtn8AHu/aKotLZ6UHVTNxFg4AHwte9fJYrZe72e6aR+8XQaCBPz47pi8 # NHAnGWWc28SdNCau7I8uMg== # =0yEm # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Nov 2022 07:59:23 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Limit LPA2 effective output address when TCR.DS == 0 tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s hw/intc: add implementation of GICD_IIDR to Arm GIC hw/intc: clean-up access to GIC multi-byte registers hw/sd: Fix sun4i allwinner-sdhost for U-Boot Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
0b710ae5c5
@ -941,7 +941,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
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gic_update(s);
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}
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static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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{
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GICState *s = (GICState *)opaque;
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uint32_t res;
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@ -955,6 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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cm = 1 << cpu;
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if (offset < 0x100) {
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if (offset == 0) { /* GICD_CTLR */
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/* We rely here on the only non-zero bits being in byte 0 */
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if (s->security_extn && !attrs.secure) {
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/* The NS bank of this register is just an alias of the
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* EnableGrp1 bit in the S bank version.
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@ -964,13 +965,26 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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return s->ctlr;
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}
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}
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if (offset == 4)
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/* Interrupt Controller Type Register */
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return ((s->num_irq / 32) - 1)
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| ((s->num_cpu - 1) << 5)
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| (s->security_extn << 10);
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if (offset < 0x08)
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if (offset == 4) {
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/* GICD_TYPER byte 0 */
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return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
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}
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if (offset == 5) {
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/* GICD_TYPER byte 1 */
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return (s->security_extn << 2);
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}
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if (offset == 8) {
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/* GICD_IIDR byte 0 */
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return 0x3b; /* Arm JEP106 identity */
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}
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if (offset == 9) {
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/* GICD_IIDR byte 1 */
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return 0x04; /* Arm JEP106 identity */
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}
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if (offset < 0x0c) {
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/* All other bytes in this range are RAZ */
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return 0;
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}
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if (offset >= 0x80) {
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/* Interrupt Group Registers: these RAZ/WI if this is an NS
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* access to a GIC with the security extensions, or if the GIC
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@ -65,7 +65,7 @@ enum {
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REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
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REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
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REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
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REG_SD_THLDC = 0x100, /* Card Threshold Control */
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REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
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REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
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REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
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REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
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@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s)
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}
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}
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static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
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{
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uint32_t res = 0;
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if (sdbus_data_ready(&s->sdbus)) {
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sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
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le32_to_cpus(&res);
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allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
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allwinner_sdhost_auto_stop(s);
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allwinner_sdhost_update_irq(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
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__func__);
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}
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return res;
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}
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static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AwSdHostState *s = AW_SDHOST(opaque);
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AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
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uint32_t res = 0;
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switch (offset) {
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@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
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case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
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res = s->dmac_irq;
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break;
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case REG_SD_THLDC: /* Card Threshold Control */
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res = s->card_threshold;
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case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
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if (sc->is_sun4i) {
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res = allwinner_sdhost_fifo_read(s);
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} else {
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res = s->card_threshold;
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}
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break;
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case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
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res = s->startbit_detect;
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@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
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res = s->status_crc;
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break;
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case REG_SD_FIFO: /* Read/Write FIFO */
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if (sdbus_data_ready(&s->sdbus)) {
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sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
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le32_to_cpus(&res);
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allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
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allwinner_sdhost_auto_stop(s);
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allwinner_sdhost_update_irq(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
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__func__);
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}
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res = allwinner_sdhost_fifo_read(s);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
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@ -553,11 +567,20 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
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return res;
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}
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static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
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{
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uint32_t u32 = cpu_to_le32(value);
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sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
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allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
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allwinner_sdhost_auto_stop(s);
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allwinner_sdhost_update_irq(s);
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}
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static void allwinner_sdhost_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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AwSdHostState *s = AW_SDHOST(opaque);
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uint32_t u32;
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AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
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trace_allwinner_sdhost_write(offset, value, size);
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@ -657,18 +680,18 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
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s->dmac_irq = value;
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allwinner_sdhost_update_irq(s);
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break;
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case REG_SD_THLDC: /* Card Threshold Control */
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s->card_threshold = value;
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case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
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if (sc->is_sun4i) {
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allwinner_sdhost_fifo_write(s, value);
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} else {
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s->card_threshold = value;
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}
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break;
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case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
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s->startbit_detect = value;
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break;
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case REG_SD_FIFO: /* Read/Write FIFO */
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u32 = cpu_to_le32(value);
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sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
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allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
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allwinner_sdhost_auto_stop(s);
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allwinner_sdhost_update_irq(s);
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allwinner_sdhost_fifo_write(s, value);
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break;
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case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
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case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
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@ -834,12 +857,14 @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
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{
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AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
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sc->max_desc_size = 8 * KiB;
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sc->is_sun4i = true;
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}
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static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
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{
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AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
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sc->max_desc_size = 64 * KiB;
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sc->is_sun4i = false;
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}
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static const TypeInfo allwinner_sdhost_info = {
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@ -130,6 +130,7 @@ struct AwSdHostClass {
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/** Maximum buffer size in bytes per DMA descriptor */
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size_t max_desc_size;
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bool is_sun4i;
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};
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@ -1222,6 +1222,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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ps = MIN(ps, param.ps);
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assert(ps < ARRAY_SIZE(pamax_map));
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outputsize = pamax_map[ps];
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/*
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* With LPA2, the effective output address (OA) size is at most 48 bits
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* unless TCR.DS == 1
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*/
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if (!param.ds && param.gran != Gran64K) {
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outputsize = MIN(outputsize, 48);
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}
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} else {
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param = aa32_va_parameters(env, address, mmu_idx);
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level = 1;
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@ -64,7 +64,7 @@ class BootLinuxAarch64(LinuxTest):
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:avocado: tags=machine:virt
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:avocado: tags=machine:gic-version=2
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"""
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timeout = 240
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timeout = 720
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def add_common_args(self):
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self.vm.add_args('-bios',
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