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target/arm: Convert Neon 2-reg-misc crypto operations to decodetree

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Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-06-16 18:08:31 +01:00
parent 75153179e9
commit 0b30dd5b85
3 changed files with 58 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target/arm/neon-dp.decode
View File

@ -441,12 +441,19 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
&2misc vm=%vm_dp vd=%vd_dp
@2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \
&2misc vm=%vm_dp vd=%vd_dp q=0
@2misc_q1 .... ... .. . .. size:2 .. .... . .... . . . .... \
&2misc vm=%vm_dp vd=%vd_dp q=1
VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
AESE 1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1
AESD 1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1
AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
@ -458,6 +465,8 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
SHA1H 1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
@ -473,6 +482,9 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
]

42
target/arm/translate-neon.inc.c
View File

@ -3505,3 +3505,45 @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a)
}
return do_2misc_vec(s, a, tcg_gen_gvec_not);
}
#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
uint32_t maxsz) \
{ \
tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \
DATA, FUNC); \
}
#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
uint32_t maxsz) \
{ \
tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \
}
WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \
static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
{ \
if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \
return false; \
} \
return do_2misc_vec(s, a, gen_##INSN); \
}
DO_2M_CRYPTO(AESE, aa32_aes, 0)
DO_2M_CRYPTO(AESD, aa32_aes, 0)
DO_2M_CRYPTO(AESMC, aa32_aes, 0)
DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)

52
target/arm/translate.c
View File

@ -4855,7 +4855,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
{
int op;
int q;
int rd, rm, rd_ofs, rm_ofs;
int rd, rm;
int size;
int pass;
int u;
@ -4882,8 +4882,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
VFP_DREG_D(rd, insn);
VFP_DREG_M(rm, insn);
size = (insn >> 20) & 3;
rd_ofs = neon_reg_offset(rd, 0);
rm_ofs = neon_reg_offset(rm, 0);
if ((insn & (1 << 23)) == 0) {
/* Three register same length: handled by decodetree */
@ -4935,6 +4933,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VCLE0:
case NEON_2RM_VCGE0:
case NEON_2RM_VCLT0:
case NEON_2RM_AESE: case NEON_2RM_AESMC:
case NEON_2RM_SHA1H:
case NEON_2RM_SHA1SU1:
/* handled by decodetree */
return 1;
case NEON_2RM_VTRN:
@ -4950,51 +4951,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
goto elementwise;
}
break;
case NEON_2RM_AESE: case NEON_2RM_AESMC:
if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
return 1;
}
/*
* Bit 6 is the lowest opcode bit; it distinguishes
* between encryption (AESE/AESMC) and decryption
* (AESD/AESIMC).
*/
if (op == NEON_2RM_AESE) {
tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aese);
} else {
tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aesmc);
}
break;
case NEON_2RM_SHA1H:
if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
return 1;
}
tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
gen_helper_crypto_sha1h);
break;
case NEON_2RM_SHA1SU1:
if ((rm | rd) & 1) {
return 1;
}
/* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
if (q) {
if (!dc_isar_feature(aa32_sha2, s)) {
return 1;
}
} else if (!dc_isar_feature(aa32_sha1, s)) {
return 1;
}
tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
q ? gen_helper_crypto_sha256su0
: gen_helper_crypto_sha1su1);
break;
default:
elementwise: