monitor/target-ppc: Define target_get_monitor_def
At the moment get_monitor_def() returns only registers from statically defined monitor_defs array. However there is a lot of BOOK3S SPRs which are not in the list and cannot be printed from the monitor. This adds a new target platform hook - target_get_monitor_def(). The hook is called if a register was not found in the static array returned by the target_monitor_defs() hook. The hook is only defined for POWERPC, it returns registered SPRs and fails on unregistered ones providing the user with information on what is actually supported on the running CPU. The register value is saved as uint64_t as it is the biggest supported register size; target_ulong cannot be used because of the stub - it is in a "common" code and cannot include "cpu.h", etc; this is also why the hook prototype is redefined in the stub instead of being included from some header. This replaces static descriptors for GPRs, FPRs, SRs with a helper which looks for a value in a corresponding array in the CPUPPCState. The immediate effect is that all 32 SRs can be printed now (instead of 16); later this can be reused for VSX or TM registers. This replaces callbacks for MSR and XER with static descriptors in monitor_defs as they are stored in CPUPPCState. While we are here, this adds "cr" as a synonym of "ccr". Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Alexey Kardashevskiy
David Gibson
parent
cffc331a31
commit
0a9516c2d6
@ -35,6 +35,7 @@ struct MonitorDef {
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};
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};
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const MonitorDef *target_monitor_defs(void);
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const MonitorDef *target_monitor_defs(void);
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int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval);
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CPUArchState *mon_get_cpu_env(void);
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CPUArchState *mon_get_cpu_env(void);
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CPUState *mon_get_cpu(void);
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CPUState *mon_get_cpu(void);
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10
monitor.c
10
monitor.c
@ -2136,6 +2136,8 @@ static int get_monitor_def(target_long *pval, const char *name)
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{
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{
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const MonitorDef *md = target_monitor_defs();
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const MonitorDef *md = target_monitor_defs();
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void *ptr;
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void *ptr;
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uint64_t tmp = 0;
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int ret;
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if (md == NULL) {
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if (md == NULL) {
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return -1;
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return -1;
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@ -2163,7 +2165,13 @@ static int get_monitor_def(target_long *pval, const char *name)
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return 0;
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return 0;
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}
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}
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}
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}
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return -1;
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ret = target_get_monitor_def(mon_get_cpu(), name, &tmp);
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if (!ret) {
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*pval = (target_long) tmp;
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}
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return ret;
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}
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}
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static void next(void)
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static void next(void)
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@ -36,4 +36,5 @@ stub-obj-y += cpus.o
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stub-obj-y += kvm.o
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stub-obj-y += kvm.o
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stub-obj-y += qmp_pc_dimm_device_list.o
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stub-obj-y += qmp_pc_dimm_device_list.o
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stub-obj-y += target-monitor-defs.o
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stub-obj-y += target-monitor-defs.o
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stub-obj-y += target-get-monitor-def.o
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stub-obj-y += vhost.o
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stub-obj-y += vhost.o
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31
stubs/target-get-monitor-def.c
Normal file
31
stubs/target-get-monitor-def.c
Normal file
@ -0,0 +1,31 @@
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/*
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* Stub for target_get_monitor_def.
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*
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* Copyright IBM Corp., 2015
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*
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* Author: Alexey Kardashevskiy <aik@ozlabs.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "stdint.h"
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typedef struct CPUState CPUState;
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int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval);
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int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
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{
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return -1;
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}
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@ -118,6 +118,8 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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int flags);
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void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
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void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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fprintf_function cpu_fprintf, int flags);
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int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
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uint64_t *pval);
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
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@ -39,18 +39,6 @@ static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
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return u;
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return u;
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}
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}
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static target_long monitor_get_msr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return env->msr;
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}
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static target_long monitor_get_xer (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return env->xer;
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}
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static target_long monitor_get_decr (const struct MonitorDef *md, int val)
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static target_long monitor_get_decr (const struct MonitorDef *md, int val)
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{
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{
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CPUArchState *env = mon_get_cpu_env();
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CPUArchState *env = mon_get_cpu_env();
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@ -76,176 +64,19 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
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dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
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}
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}
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const MonitorDef monitor_defs[] = {
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const MonitorDef monitor_defs[] = {
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/* General purpose registers */
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{ "r0", offsetof(CPUPPCState, gpr[0]) },
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{ "r1", offsetof(CPUPPCState, gpr[1]) },
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{ "r2", offsetof(CPUPPCState, gpr[2]) },
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{ "r3", offsetof(CPUPPCState, gpr[3]) },
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{ "r4", offsetof(CPUPPCState, gpr[4]) },
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{ "r5", offsetof(CPUPPCState, gpr[5]) },
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{ "r6", offsetof(CPUPPCState, gpr[6]) },
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{ "r7", offsetof(CPUPPCState, gpr[7]) },
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{ "r8", offsetof(CPUPPCState, gpr[8]) },
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{ "r9", offsetof(CPUPPCState, gpr[9]) },
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{ "r10", offsetof(CPUPPCState, gpr[10]) },
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{ "r11", offsetof(CPUPPCState, gpr[11]) },
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{ "r12", offsetof(CPUPPCState, gpr[12]) },
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{ "r13", offsetof(CPUPPCState, gpr[13]) },
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{ "r14", offsetof(CPUPPCState, gpr[14]) },
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{ "r15", offsetof(CPUPPCState, gpr[15]) },
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{ "r16", offsetof(CPUPPCState, gpr[16]) },
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{ "r17", offsetof(CPUPPCState, gpr[17]) },
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{ "r18", offsetof(CPUPPCState, gpr[18]) },
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{ "r19", offsetof(CPUPPCState, gpr[19]) },
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{ "r20", offsetof(CPUPPCState, gpr[20]) },
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{ "r21", offsetof(CPUPPCState, gpr[21]) },
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{ "r22", offsetof(CPUPPCState, gpr[22]) },
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{ "r23", offsetof(CPUPPCState, gpr[23]) },
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{ "r24", offsetof(CPUPPCState, gpr[24]) },
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{ "r25", offsetof(CPUPPCState, gpr[25]) },
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{ "r26", offsetof(CPUPPCState, gpr[26]) },
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{ "r27", offsetof(CPUPPCState, gpr[27]) },
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{ "r28", offsetof(CPUPPCState, gpr[28]) },
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{ "r29", offsetof(CPUPPCState, gpr[29]) },
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{ "r30", offsetof(CPUPPCState, gpr[30]) },
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{ "r31", offsetof(CPUPPCState, gpr[31]) },
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/* Floating point registers */
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{ "f0", offsetof(CPUPPCState, fpr[0]) },
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{ "f1", offsetof(CPUPPCState, fpr[1]) },
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{ "f2", offsetof(CPUPPCState, fpr[2]) },
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{ "f3", offsetof(CPUPPCState, fpr[3]) },
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{ "f4", offsetof(CPUPPCState, fpr[4]) },
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{ "f5", offsetof(CPUPPCState, fpr[5]) },
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{ "f6", offsetof(CPUPPCState, fpr[6]) },
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{ "f7", offsetof(CPUPPCState, fpr[7]) },
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{ "f8", offsetof(CPUPPCState, fpr[8]) },
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{ "f9", offsetof(CPUPPCState, fpr[9]) },
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{ "f10", offsetof(CPUPPCState, fpr[10]) },
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{ "f11", offsetof(CPUPPCState, fpr[11]) },
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{ "f12", offsetof(CPUPPCState, fpr[12]) },
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{ "f13", offsetof(CPUPPCState, fpr[13]) },
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{ "f14", offsetof(CPUPPCState, fpr[14]) },
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{ "f15", offsetof(CPUPPCState, fpr[15]) },
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{ "f16", offsetof(CPUPPCState, fpr[16]) },
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{ "f17", offsetof(CPUPPCState, fpr[17]) },
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{ "f18", offsetof(CPUPPCState, fpr[18]) },
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{ "f19", offsetof(CPUPPCState, fpr[19]) },
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{ "f20", offsetof(CPUPPCState, fpr[20]) },
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{ "f21", offsetof(CPUPPCState, fpr[21]) },
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{ "f22", offsetof(CPUPPCState, fpr[22]) },
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{ "f23", offsetof(CPUPPCState, fpr[23]) },
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{ "f24", offsetof(CPUPPCState, fpr[24]) },
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{ "f25", offsetof(CPUPPCState, fpr[25]) },
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{ "f26", offsetof(CPUPPCState, fpr[26]) },
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{ "f27", offsetof(CPUPPCState, fpr[27]) },
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{ "f28", offsetof(CPUPPCState, fpr[28]) },
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{ "f29", offsetof(CPUPPCState, fpr[29]) },
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{ "f30", offsetof(CPUPPCState, fpr[30]) },
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{ "f31", offsetof(CPUPPCState, fpr[31]) },
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{ "fpscr", offsetof(CPUPPCState, fpscr) },
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{ "fpscr", offsetof(CPUPPCState, fpscr) },
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/* Next instruction pointer */
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/* Next instruction pointer */
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{ "nip|pc", offsetof(CPUPPCState, nip) },
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{ "nip|pc", offsetof(CPUPPCState, nip) },
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{ "lr", offsetof(CPUPPCState, lr) },
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{ "lr", offsetof(CPUPPCState, lr) },
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{ "ctr", offsetof(CPUPPCState, ctr) },
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{ "ctr", offsetof(CPUPPCState, ctr) },
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{ "decr", 0, &monitor_get_decr, },
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{ "decr", 0, &monitor_get_decr, },
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{ "ccr", 0, &monitor_get_ccr, },
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{ "ccr|cr", 0, &monitor_get_ccr, },
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/* Machine state register */
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/* Machine state register */
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{ "msr", 0, &monitor_get_msr, },
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{ "xer", offsetof(CPUPPCState, xer) },
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{ "xer", 0, &monitor_get_xer, },
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{ "msr", offsetof(CPUPPCState, msr) },
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{ "tbu", 0, &monitor_get_tbu, },
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{ "tbu", 0, &monitor_get_tbu, },
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{ "tbl", 0, &monitor_get_tbl, },
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{ "tbl", 0, &monitor_get_tbl, },
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/* Segment registers */
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{ "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
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{ "sr0", offsetof(CPUPPCState, sr[0]) },
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{ "sr1", offsetof(CPUPPCState, sr[1]) },
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{ "sr2", offsetof(CPUPPCState, sr[2]) },
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{ "sr3", offsetof(CPUPPCState, sr[3]) },
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{ "sr4", offsetof(CPUPPCState, sr[4]) },
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{ "sr5", offsetof(CPUPPCState, sr[5]) },
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{ "sr6", offsetof(CPUPPCState, sr[6]) },
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{ "sr7", offsetof(CPUPPCState, sr[7]) },
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{ "sr8", offsetof(CPUPPCState, sr[8]) },
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{ "sr9", offsetof(CPUPPCState, sr[9]) },
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{ "sr10", offsetof(CPUPPCState, sr[10]) },
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{ "sr11", offsetof(CPUPPCState, sr[11]) },
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{ "sr12", offsetof(CPUPPCState, sr[12]) },
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{ "sr13", offsetof(CPUPPCState, sr[13]) },
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{ "sr14", offsetof(CPUPPCState, sr[14]) },
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{ "sr15", offsetof(CPUPPCState, sr[15]) },
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/* Too lazy to put BATs... */
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{ "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
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{ "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
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{ "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
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{ "dar", offsetof(CPUPPCState, spr[SPR_DAR]) },
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{ "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) },
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{ "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) },
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{ "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
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{ "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
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{ "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
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{ "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
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{ "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
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{ "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
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{ "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
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{ "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
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{ "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
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{ "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
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{ "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
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{ "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
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{ "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
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{ "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
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{ "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
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{ "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
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{ "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
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{ "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
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{ "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
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{ "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
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{ "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
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{ "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
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{ "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
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{ "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
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{ "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
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{ "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
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{ "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
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{ "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
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{ "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
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{ "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
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{ "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
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{ "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
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{ "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
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{ "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
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{ "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
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{ "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
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{ "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
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{ "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
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{ "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
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{ "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
|
|
||||||
{ "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
|
|
||||||
{ "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
|
|
||||||
{ "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
|
|
||||||
{ "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
|
|
||||||
{ "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
|
|
||||||
{ "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
|
|
||||||
{ "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
|
|
||||||
{ "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
|
|
||||||
{ "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
|
|
||||||
{ "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
|
|
||||||
{ "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
|
|
||||||
{ "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
|
|
||||||
{ "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
|
|
||||||
{ "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
|
|
||||||
{ "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
|
|
||||||
{ "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
|
|
||||||
{ "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
|
|
||||||
{ "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
|
|
||||||
{ "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
|
|
||||||
{ "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
|
|
||||||
{ "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
|
|
||||||
{ "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
|
|
||||||
{ "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
|
|
||||||
{ "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
|
|
||||||
{ NULL },
|
{ NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -253,3 +84,63 @@ const MonitorDef *target_monitor_defs(void)
|
|||||||
{
|
{
|
||||||
return monitor_defs;
|
return monitor_defs;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
|
||||||
|
{
|
||||||
|
int regnum;
|
||||||
|
char *endptr = NULL;
|
||||||
|
|
||||||
|
if (!*numstr) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
regnum = strtoul(numstr, &endptr, 10);
|
||||||
|
if (*endptr || (regnum >= maxnum)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
*pregnum = regnum;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
|
||||||
|
{
|
||||||
|
int i, regnum;
|
||||||
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
||||||
|
CPUPPCState *env = &cpu->env;
|
||||||
|
|
||||||
|
/* General purpose registers */
|
||||||
|
if ((tolower(name[0]) == 'r') &&
|
||||||
|
ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {
|
||||||
|
*pval = env->gpr[regnum];
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Floating point registers */
|
||||||
|
if ((tolower(name[0]) == 'f') &&
|
||||||
|
ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->fpr), ®num)) {
|
||||||
|
*pval = env->fpr[regnum];
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Special purpose registers */
|
||||||
|
for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
|
||||||
|
ppc_spr_t *spr = &env->spr_cb[i];
|
||||||
|
|
||||||
|
if (spr->name && (strcasecmp(name, spr->name) == 0)) {
|
||||||
|
*pval = env->spr[i];
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Segment registers */
|
||||||
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
|
if ((strncasecmp(name, "sr", 2) == 0) &&
|
||||||
|
ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {
|
||||||
|
*pval = env->sr[regnum];
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user