target/arm: Pass memop to gen_mte_check1*
Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230530191438.411344-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
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03176bcd03
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0a9091424d
@ -253,7 +253,7 @@ static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
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*/
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*/
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static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
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static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
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bool is_write, bool tag_checked,
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bool is_write, bool tag_checked,
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int log2_size, bool is_unpriv,
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MemOp memop, bool is_unpriv,
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int core_idx)
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int core_idx)
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{
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{
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if (tag_checked && s->mte_active[is_unpriv]) {
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if (tag_checked && s->mte_active[is_unpriv]) {
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@ -264,7 +264,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
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desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1);
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ret = tcg_temp_new_i64();
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ret = tcg_temp_new_i64();
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gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
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gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
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@ -275,9 +275,9 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
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}
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}
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TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int log2_size)
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bool tag_checked, MemOp memop)
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{
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{
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return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size,
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return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, memop,
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false, get_mem_index(s));
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false, get_mem_index(s));
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}
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}
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@ -2369,19 +2369,31 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn,
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int size, bool is_pair)
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int size, bool is_pair)
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{
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{
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int idx = get_mem_index(s);
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int idx = get_mem_index(s);
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MemOp memop;
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TCGv_i64 dirty_addr, clean_addr;
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TCGv_i64 dirty_addr, clean_addr;
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MemOp memop;
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/*
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* For pairs:
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* if size == 2, the operation is single-copy atomic for the doubleword.
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* if size == 3, the operation is single-copy atomic for *each* doubleword,
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* not the entire quadword, however it must be quadword aligned.
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*/
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memop = size + is_pair;
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if (memop == MO_128) {
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memop = finalize_memop_atom(s, MO_128 | MO_ALIGN,
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MO_ATOM_IFALIGN_PAIR);
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} else {
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memop = finalize_memop(s, memop | MO_ALIGN);
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}
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s->is_ldex = true;
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s->is_ldex = true;
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dirty_addr = cpu_reg_sp(s, rn);
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dirty_addr = cpu_reg_sp(s, rn);
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clean_addr = gen_mte_check1(s, dirty_addr, false, rn != 31, size);
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clean_addr = gen_mte_check1(s, dirty_addr, false, rn != 31, memop);
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g_assert(size <= 3);
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g_assert(size <= 3);
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if (is_pair) {
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if (is_pair) {
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g_assert(size >= 2);
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g_assert(size >= 2);
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if (size == 2) {
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if (size == 2) {
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/* The pair must be single-copy atomic for the doubleword. */
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memop = finalize_memop(s, MO_64 | MO_ALIGN);
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop);
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop);
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if (s->be_data == MO_LE) {
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if (s->be_data == MO_LE) {
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tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);
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tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);
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@ -2391,16 +2403,8 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn,
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tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32);
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tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32);
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}
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}
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} else {
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} else {
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/*
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* The pair must be single-copy atomic for *each* doubleword, not
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* the entire quadword, however it must be quadword aligned.
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* Expose the complete load to tcg, for ease of tlb lookup,
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* but indicate that only 8-byte atomicity is required.
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*/
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TCGv_i128 t16 = tcg_temp_new_i128();
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TCGv_i128 t16 = tcg_temp_new_i128();
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memop = finalize_memop_atom(s, MO_128 | MO_ALIGN_16,
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MO_ATOM_IFALIGN_PAIR);
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tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop);
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tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop);
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if (s->be_data == MO_LE) {
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if (s->be_data == MO_LE) {
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@ -2414,7 +2418,6 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn,
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tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
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tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
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}
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}
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} else {
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} else {
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memop = finalize_memop(s, size | MO_ALIGN);
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop);
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop);
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tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
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tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
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}
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}
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@ -2439,9 +2442,13 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGLabel *fail_label = gen_new_label();
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TCGLabel *fail_label = gen_new_label();
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TCGLabel *done_label = gen_new_label();
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TCGLabel *done_label = gen_new_label();
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TCGv_i64 tmp, dirty_addr, clean_addr;
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TCGv_i64 tmp, dirty_addr, clean_addr;
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MemOp memop;
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memop = (size + is_pair) | MO_ALIGN;
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memop = finalize_memop(s, memop);
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dirty_addr = cpu_reg_sp(s, rn);
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dirty_addr = cpu_reg_sp(s, rn);
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clean_addr = gen_mte_check1(s, dirty_addr, true, rn != 31, size);
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clean_addr = gen_mte_check1(s, dirty_addr, true, rn != 31, memop);
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tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_label);
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tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_label);
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@ -2455,8 +2462,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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}
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}
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tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
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tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
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cpu_exclusive_val, tmp,
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cpu_exclusive_val, tmp,
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get_mem_index(s),
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get_mem_index(s), memop);
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MO_64 | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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} else {
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} else {
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TCGv_i128 t16 = tcg_temp_new_i128();
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TCGv_i128 t16 = tcg_temp_new_i128();
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@ -2474,8 +2480,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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}
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}
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tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16,
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tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16,
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get_mem_index(s),
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get_mem_index(s), memop);
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MO_128 | MO_ALIGN | s->be_data);
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a = tcg_temp_new_i64();
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a = tcg_temp_new_i64();
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b = tcg_temp_new_i64();
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b = tcg_temp_new_i64();
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@ -2493,8 +2498,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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}
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}
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} else {
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} else {
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tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
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tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
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cpu_reg(s, rt), get_mem_index(s),
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cpu_reg(s, rt), get_mem_index(s), memop);
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size | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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}
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}
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tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
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tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
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@ -2513,13 +2517,15 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt,
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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TCGv_i64 tcg_rt = cpu_reg(s, rt);
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int memidx = get_mem_index(s);
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int memidx = get_mem_index(s);
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TCGv_i64 clean_addr;
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TCGv_i64 clean_addr;
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MemOp memop;
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if (rn == 31) {
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if (rn == 31) {
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gen_check_sp_alignment(s);
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gen_check_sp_alignment(s);
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}
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}
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size);
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memop = finalize_memop(s, size | MO_ALIGN);
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tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx,
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop);
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size | MO_ALIGN | s->be_data);
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tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt,
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memidx, memop);
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}
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}
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static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
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static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
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@ -2531,13 +2537,15 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
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TCGv_i64 t2 = cpu_reg(s, rt + 1);
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TCGv_i64 t2 = cpu_reg(s, rt + 1);
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TCGv_i64 clean_addr;
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TCGv_i64 clean_addr;
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int memidx = get_mem_index(s);
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int memidx = get_mem_index(s);
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MemOp memop;
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if (rn == 31) {
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if (rn == 31) {
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gen_check_sp_alignment(s);
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gen_check_sp_alignment(s);
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}
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}
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/* This is a single atomic access, despite the "pair". */
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/* This is a single atomic access, despite the "pair". */
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size + 1);
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memop = finalize_memop(s, (size + 1) | MO_ALIGN);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop);
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if (size == 2) {
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if (size == 2) {
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TCGv_i64 cmp = tcg_temp_new_i64();
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TCGv_i64 cmp = tcg_temp_new_i64();
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@ -2551,8 +2559,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
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tcg_gen_concat32_i64(cmp, s2, s1);
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tcg_gen_concat32_i64(cmp, s2, s1);
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}
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}
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tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx,
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tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, memop);
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MO_64 | MO_ALIGN | s->be_data);
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if (s->be_data == MO_LE) {
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if (s->be_data == MO_LE) {
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tcg_gen_extr32_i64(s1, s2, cmp);
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tcg_gen_extr32_i64(s1, s2, cmp);
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@ -2571,8 +2578,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
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tcg_gen_concat_i64_i128(cmp, s2, s1);
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tcg_gen_concat_i64_i128(cmp, s2, s1);
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}
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}
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tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx,
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tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, memop);
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MO_128 | MO_ALIGN | s->be_data);
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if (s->be_data == MO_LE) {
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if (s->be_data == MO_LE) {
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tcg_gen_extr_i128_i64(s1, s2, cmp);
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tcg_gen_extr_i128_i64(s1, s2, cmp);
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@ -2661,7 +2667,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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memop = finalize_memop(s, size | MO_ALIGN);
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memop = finalize_memop(s, size | MO_ALIGN);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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true, rn != 31, size);
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true, rn != 31, memop);
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do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt,
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do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt,
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disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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return;
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return;
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@ -2680,7 +2686,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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/* TODO: ARMv8.4-LSE SCTLR.nAA */
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memop = finalize_memop(s, size | MO_ALIGN);
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memop = finalize_memop(s, size | MO_ALIGN);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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false, rn != 31, size);
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false, rn != 31, memop);
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true,
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true,
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rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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@ -3223,7 +3229,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
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tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
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tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, memop);
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if (is_vector) {
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if (is_vector) {
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if (is_store) {
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if (is_store) {
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@ -3309,7 +3315,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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memop = finalize_memop(s, size + is_signed * MO_SIGN);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size);
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clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop);
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if (is_vector) {
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if (is_vector) {
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if (is_store) {
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if (is_store) {
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@ -3404,7 +3410,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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if (rn == 31) {
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if (rn == 31) {
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gen_check_sp_alignment(s);
|
gen_check_sp_alignment(s);
|
||||||
}
|
}
|
||||||
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size);
|
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, mop);
|
||||||
|
|
||||||
if (o3_opc == 014) {
|
if (o3_opc == 014) {
|
||||||
/*
|
/*
|
||||||
@ -3491,7 +3497,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
|
|||||||
|
|
||||||
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
|
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
|
||||||
clean_addr = gen_mte_check1(s, dirty_addr, false,
|
clean_addr = gen_mte_check1(s, dirty_addr, false,
|
||||||
is_wback || rn != 31, size);
|
is_wback || rn != 31, memop);
|
||||||
|
|
||||||
tcg_rt = cpu_reg(s, rt);
|
tcg_rt = cpu_reg(s, rt);
|
||||||
do_gpr_ld(s, tcg_rt, clean_addr, memop,
|
do_gpr_ld(s, tcg_rt, clean_addr, memop,
|
||||||
|
@ -49,7 +49,7 @@ static inline bool sme_smza_enabled_check(DisasContext *s)
|
|||||||
|
|
||||||
TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
|
TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
|
||||||
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
|
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
|
||||||
bool tag_checked, int log2_size);
|
bool tag_checked, MemOp memop);
|
||||||
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
|
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
|
||||||
bool tag_checked, int size);
|
bool tag_checked, int size);
|
||||||
|
|
||||||
|
@ -5009,6 +5009,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
|
|||||||
unsigned msz = dtype_msz(a->dtype);
|
unsigned msz = dtype_msz(a->dtype);
|
||||||
TCGLabel *over;
|
TCGLabel *over;
|
||||||
TCGv_i64 temp, clean_addr;
|
TCGv_i64 temp, clean_addr;
|
||||||
|
MemOp memop;
|
||||||
|
|
||||||
if (!dc_isar_feature(aa64_sve, s)) {
|
if (!dc_isar_feature(aa64_sve, s)) {
|
||||||
return false;
|
return false;
|
||||||
@ -5038,10 +5039,10 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
|
|||||||
/* Load the data. */
|
/* Load the data. */
|
||||||
temp = tcg_temp_new_i64();
|
temp = tcg_temp_new_i64();
|
||||||
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
|
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
|
||||||
clean_addr = gen_mte_check1(s, temp, false, true, msz);
|
|
||||||
|
|
||||||
tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s),
|
memop = finalize_memop(s, dtype_mop[a->dtype]);
|
||||||
finalize_memop(s, dtype_mop[a->dtype]));
|
clean_addr = gen_mte_check1(s, temp, false, true, memop);
|
||||||
|
tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), memop);
|
||||||
|
|
||||||
/* Broadcast to *all* elements. */
|
/* Broadcast to *all* elements. */
|
||||||
tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),
|
tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),
|
||||||
|
Loading…
Reference in New Issue
Block a user