target/riscv: Add support for disabling/enabling Counters

Add support for disabling/enabling the "Counters" extension.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Alistair Francis 2019-06-17 18:31:22 -07:00 committed by Palmer Dabbelt
parent c9a73910c3
commit 0a13a5b856
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
3 changed files with 14 additions and 5 deletions

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@ -440,6 +440,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),

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@ -222,6 +222,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_counters;
char *priv_spec;
char *user_spec;

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@ -56,17 +56,24 @@ static int fs(CPURISCVState *env, int csrno)
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t ctr_en = ~0u;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return -1;
}
/*
* The counters are always enabled on newer priv specs, as the CSR has
* changed from controlling that the counters can be read to controlling
* that the counters increment.
* The counters are always enabled at run time on newer priv specs, as the
* CSR has changed from controlling that the counters can be read to
* controlling that the counters increment.
*/
if (env->priv_ver > PRIV_VERSION_1_09_1) {
return 0;
}
uint32_t ctr_en = ~0u;
if (env->priv < PRV_M) {
ctr_en &= env->mcounteren;
}